하드웨어 구조 변경을 통한 마이크로프로세서 내부 명령어 캐쉬에서의 동적 전력 소모 감소 기법

Architecture-Level Approaches for Reducing the Dynamic Power Consumption in Instruction Caches

  • 발행 : 2012.07.16

초록

키워드

참고문헌

  1. K. Ghose and M. B. Kamble, Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers and Bit-line Segmentation, International Symposium on Low Power Electronics and Design, 1999
  2. M. B. Kamble and K. Ghose, Analytical Energy Dissipation Models for Low-Power Caches, International Symposium on Low Power Electronics and Design, 1997
  3. A. Ma, M. Zhang, and K. Asanovic, Way Memorization to Reduce Fetch Energy in Instruction Caches, Workshop on Complexity-Effective Design, 2001
  4. E. Witchel and K. Asanovic, The Span Cache: Software Controlled Tag Checks and Cache Line Size, Workshop on Complexity-Effective Design, 2001
  5. S. Segars, Low Power Design Techniques for Microprocessors, International Solid-State Circuits Conference, 2001
  6. J. Kin, M. Gupta, and W. Mangione-Smith, The Filter Cache: An Energy Efficient Memory Structure, International Symposium on Microarchitecture, 1997
  7. N. Bellas, I. Hajj, and C. Poiychronopoulos, Using Dynamic Cache Management Techniques to Reduce Energy in a High-performance Processor, International Symposium on Low Power Electronics and Design, 1999
  8. David H. Albonesi, Selective Cache Ways: On-Demand Cache Resource Allocation, International Symposium on Microarchitecture, 1999
  9. M. Powell, A. Agarwal, T. N. Vijaykumar, B. Falsafi, and K. Roy, Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping, Proceedings of International Symposium on Microarchitecture, 2001