Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
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Multi-Level Groupings of Minterms Using the Decimal-Valued Matrix Method

십진수로 표현된 매트릭스에 의한 최소항의 다층모형 그룹화

  • Kim, Eun-Gi (Dept. of Information Communication Engineering, NamSeoul University)
  • 김은기 (남서울대학교 정보통신공학과)
  • Received : 2012.03.09
  • Accepted : 2012.05.04
  • Published : 2012.06.30
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Abstract

This paper suggests an improved method of grouping minterms based on the Decimal-Valued Matrix (DVM) method. The DVM is a novel approach to Boolean logic minimization method which was recently developed by this author. Using the minterm-based matrix layout, the method captures binary number based minterm differences in decimal number form. As a result, combinable minterms can be visually identified. Furthermore, they can be systematically processed in finding a minimized Boolean expression. Although this new matrix based approach is visual-based, the suggested method in symmetric grouping cell values can become rather messy in some cases. To alleviate this problem, the enhanced DVM method that is based on multi-level groupings of combinable minterms is presented in this paper. Overall, since the method described here provides a concise visualization of minterm groupings, it facilitates a user with more options to explore different combinable minterm groups for a given Boolean logic minimization problem.

이 논문에서는 십진수의 매트릭스 방법 (DVM) 을 이용한 새로운 방법으로 불리언 논리를 최소화할 때 최소항을 그룹화 하여 표시하는 방법을 제안하고 있다. DVM 방법은 매트릭스 방법을 이용하여 최소항에 관한 이진수의 차이를 십진수 형태로 변환하는 과정을 거치고, 결합할 수 있는 최소항을 직접 확인할 수 있다. 십진수의 매트릭스 방법은 시각적 접근에 따른 새로운 매트릭스이지만, 경우에 따라 주어진 셀 값을 그룹화 하는데 있어서 도형이 복잡해지기도 하는 문제점이 있다. 이 논문은 이러한 문제점을 해결하기 위한 연구로, 십진수의 매트릭스 방법에 최소항의 다단계 그룹을포함하는 기법을 제안하고 있다. 이 연구에서 제시하는 방법은 최소항의 그룹을 간결한 시각적인 방법으로 표현 하였으므로, 관련된 최소항을 구체적으로 파악하는 수단으로 사용할 수 있다.

Keywords

References

  1. M. Karnaugh, "A Map Method for Synthesis of Combinational Logic Circuits," Transactions of the AIEE, Communications and Electronics, Vol. 72, pp. 593-599, 1953.
  2. E. J. McCluskey, "Minimization of Boolean functions," Bell System Tech. Journal, Vol. 35, No. 5, pp. 1417-1444, 1956. https://doi.org/10.1002/j.1538-7305.1956.tb03835.x
  3. R. E. Bryant, "Graph-based algorithms for Boolean functions manipulation," IEEE Trans. on Computers, C-35, No 8, pp. 677-692, Aug., 1986. https://doi.org/10.1109/TC.1986.1676819
  4. O. Coudert and J. C. Madre, "Implicit and incremental computation of primes and essential primes of Boolean functions," Proc. 29th DAC, CA, USA, pp. 36-39, June 1992.
  5. R. L. Rudell, Logic Synthesis for VLSI Design, Ph.D. Dissertation, UCB/ERL M89/49, 1989.
  6. F. Basciftci, "Simplification of Single-Output Boolean Functions by Exact Direct Cover Algorithm Based on Cube Algebra," EUROCON, pp. 427-431, Sept. 2007.
  7. A. Dusa, "Enhancing Quine-McCluskey," 2007. http://www.compasss.org/files/WPfiles/Dusa2007a.pdf (Accessed: 9 February 2012).
  8. A. Dusa, "A Mathematical Approach to the Boolean Minimization Problem," Quality & Quantity, Vol. 44, No. 1, pp. 99-113. 2010. https://doi.org/10.1007/s11135-008-9183-x
  9. P. Fiser, P. Rucky, and I. Vanova, "Fast Boolean Minimizer for Completely Specified Functions", Proc. 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008, Bratislava, SK, pp. 122-127.
  10. J. Hlavicka and P. Fiser. "BOOM-A Heuristic Boolean Minimizer," Computers and Artificial Intelligence Vol. 22, No 1. pp. 19-51, 2003.
  11. P. W. C. Prasad, A. Beg, and A. K. Singh, "Effect of Quine-McCluskey Simplification on Boolean Space Complexity, IEEE Proceeding 2009 Conference on Innovative Technologies in Intelligent Systems and Industrial Applications, pp. 165-170, Monash University, July, 2009.
  12. D. Toman and P. Fiser. "A SOP Minimizer for Logic Functions Described by Many Product Terms Based on Ternary Trees," In Proceedings of 9th International Workshop on Boolean Problems (IWSBP), 2010.
  13. E. Kim. "A Visual-Based Logic Minimization Method," Journal of the Korea Industrial Information Systems Research, Vol. 16, No 5, Dec., 2011.
  14. B. Holdsworth and C. Wood, Digital Logic Design, 4th ed., Newnes, 2002.
  15. C. H. Roth, Jr., Fundamentals of Logic Design, 5th ed., Thomson Engineering, 2004.
  16. P. K. Lala, Principles of Modern Digital Design, John Wiley & Sons, Inc., Hoboken, NJ, USA., 2006.
  17. C. Umans, T. Villa, and A.L. Sangiovanni-Vincentelli, "Complexity of Two-Level Logic Minimization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems. Vol. 25, No. 7, pp. 1230-1246, 2006. https://doi.org/10.1109/TCAD.2005.855944