DOI QR코드

DOI QR Code

The resistance characterization of OTP device using anti-fuse MOS capacitor after programming

안티퓨즈 MOS capacitor를 이용한 OTP 소자의 프로그래밍 후의 저항특성

  • Chang, Sung-Keun (Dept. of Electronics Engineering, Chungwoon University) ;
  • Kim, Youn-Jang (The Research Institute for Basic Sciences, Changwon National University)
  • 장성근 (청운대학교 전자공학과) ;
  • 김윤장 (국립창원대학교 기초과학연구소)
  • Received : 2012.03.15
  • Accepted : 2012.06.07
  • Published : 2012.06.30

Abstract

The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.

안티퓨즈 MOS 커패시터를 기반으로 제작된 OTP 소자의 수율은 프로그램 과정에서 입력 저항(Rin)값과 통과 트랜지스터(Pass Tr)의 크기, 데이터 읽기 과정에서 읽기 트랜지스터(Read Tr)와 읽기 전압에 영향을 받는다. 따라서 수율에 영향을 주는 요소를 분석하기 위해 여러 가지 실험 조건을 달리하여 각각의 조건에 대해 블로잉 후 실효소자의 저항 특성에 대한 풀 맵(full map) 데이터를 얻어 OTP 소자가 어떻게 동작하는지를 분석하여 수율 개선에 필요한 최적 조건을 연구하였다. 최적 조건은 입력저항이 $50{\Omega}$, 통과 트랜지스터의 W값이 $10{\mu}m$, 읽기 전압이 2.8 V 일 때이다.

Keywords

References

  1. L. J. Tang, K. L. Pey, C. H. Tung, M. K. Radhakrishnan, and W. H. Lin, "Gate Dielectric-Breakdown-Induced Microstructural Damage in MOSFETs", IEEE Trans. on device and materials Rel. Vol. 4 No. 1 p. 38, 2004. https://doi.org/10.1109/TDMR.2004.824374
  2. N. Mathur, Y. Ahn, I. Kouznetove, F. Jenne, J. Fulford, "One Time programming Device Yield Study Based On Anti-Fuse Gate Oxide breakdown on P-type and N-type Substrates", IEEE IIRW p. 111, 2005.
  3. R. Degraeve, A. D. Keersgieter, G. Groeseneken, "Relationship between Breakdown Mode And Breakdown Location in Short Channel NMOSFETs and its impact on reliability specifications", IEEE 39th Annual International Reliability Physics Symposium, p. 360, 2001.
  4. Hee Eng Gek, Chee Boon Jiew, Alexander Tan Chuan Chien and Seok Sewoon, "Influence of Conformal Nitride Material Impacting the OTP & MTP Data Retention Performance", IEEE ICSE Proc, p.383, 2008
  5. J. Peng, G. Rosendale, M. Fliesler, D. Fong, J. Wang, C. Ng, ZS Liu, Harry Luan, "A Novel Embedded OTP NVM Using Standard Foundry CMOS Logic Technology", IEEE NVSMW p.24, 2006.
  6. Tsung-Yu Chiang, Ming-Wen Ma, Yi-Hong Wu, Po-Yi Kuo, Kuan-Ti Wang, "MILC-TFT With High-$\kappa$ Dielectrics for One-Time-Programmable Memory Application", IEEE Electron Device lett. p.954, 2009.