IEMEK Journal of Embedded Systems and Applications (대한임베디드공학회논문지)

Institute of Embedded Engineering of Korea (대한임베디드공학회)
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An Efficient Implementation Architecture for Lifting Based High Speed Integer Wavelet Transform

리프팅 기반의 고속 정수 웨이블릿 변환의 효율적인 구현 구조

  • Received : 2012.01.27
  • Accepted : 2012.04.09
  • Published : 2012.08.31
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Abstract

In this paper, we propose an efficient architecture for 2D IWT using an existing 1D IWT. Lifting based IWT is the architecture of which a multiplier is replaced by adders and shift registers. The structure is relatively simple and modular. The proposed architecture to process an image size with 256x256 pixels consists of 16 adders, 8 shift registers, and some memories. By processing two rows at the same time, 2D sub-band coefficients can be calculated immediately after 1D sub-band coefficients have been processed. The architecture is designed so that each image can be inputted consecutively. The number of adders and shift registers is increased by twice comparing the existing architecture, but the memory size and the execution time are decreased by half. The proposed architecture is implemented using Verilog-HDL and simulated using iSim. It is synthesized and demonstrated at ISE for xc5vlx330 in RPS3K board.

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References

  1. M. Boliek, "JPEG 2000 Part I Final Draft International Standard," ISO/IEC JTC1/SC29 WG1, 2000.
  2. G. Knowles, "VLSI Architecture for the Discrete Wavelet Transform," IEEE Electronic Letters, Vol. 26, No. 15, pp.1184-1185, 1990. https://doi.org/10.1049/el:19900766
  3. I. Daubechies, W. Sweldens, "Factoring wavelet transforms into lifting steps," Preprint, Bell Lab. 1996.
  4. A.R. Calderbank, I. Daubechies, W. Sweldens, B. Yeo, "Wavelet transforms that map integers to integers," Technical Reports, Depart. of Mathematics, Princeton University, 1996.
  5. C. Hunag, P. Tseng, L. Chen, "Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method," Proceedings on IEEE International Symposium Circuits and Systems, Vol. 5, pp. 565-568. 2002.
  6. B. Wu, C. Lin, "A high-performance and memory efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec," IEEE Transactions on Circuits and Systems for Video Technology, Vol. 15, No. 12, pp.1615-628, 2005.
  7. T. Acharya, "A Survey on Lifting-based Discrete Wavelet Transform Architectures," Journal of VLSI Signal Process, Vol. 42, No. 3, pp.312-339, 2006.
  8. B. Harish, "FPGA Implementation of Multiplierless 5/3 Legal Discrete Wavelet Transform Using Lifting Approach," Proceedings on the International Conference & Workshop on Emerging Trends in Technology, pp.1066-1071, 2011.
  9. A.K. Al-Sulaifanie, A. Ahmadi, M. Zwolinski, "Very large scale integration architecture for integer wavelet transform," IET Computers and Digital Techniques, Vol. 4, No. 6, pp.471-483, 2009.
  10. K. Andra, "A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform," IEEE Transactions on Signal Processing, Vol. 50, No. 4, pp.966-977, 2002. https://doi.org/10.1109/78.992147