대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

MLC NAND-형 플래시 메모리를 위한 고장검출 테스트 알고리즘

Fault Test Algorithm for MLC NAND-type Flash Memory

  • 투고 : 2012.02.20
  • 심사 : 2012.03.30
  • 발행 : 2012.04.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

임베디드 시스템의 저장매체 시장에서 플래시 메모리가 점유율을 높여나가고 시스템 내에서 대부분의 면적을 차지하게 되면서, 시스템 신뢰도에 무거운 영향을 미치고 있다. 플래시 메모 리는 셀 배열구조에 따라 NOR/NAND-형으로 나뉘어져 있고 플로팅 게이트 셀의 Reference 전압의 갯수 따라 SLC(Single Level Cell)와 MLC(Multi Level Cell)로 구분된다. NAND-형 플래시 메모리는 NOR-형에 비해 속도는 느린 편이지만 대용량화가 쉽고 가격이 저렴하다. 또한 MLC NAND-형 플래시 메모리는 대용량 메모리의 수요가 급격히 높아진 모바일 시장의 영향으로 멀티미디어 데이터 저장의 목적으로 널리 채용되고 있다. 이에 따라 MLC NAND-형 플래시 메모리의 신뢰성을 보장하기 위해 고장 검출 테스팅의 중요도 커지고 있다. 전통적인 RAM에서부터 SLC 플래시 메모리를 위한 테스팅 알고리즘은 많은 연구가 있었고 많은 고장을 검출해 내었다. 하지만 MLC 플래시 메모리의 경우 고장검출을 위한 테스팅 시도가 많지 않았기 때문에 본 논문은 SLC NAND-형 플래시 메모리에서 제안된 기법을 확장한 MLC NAND-형 플래시 메모리를 위한 고장검출 알고리즘을 제안하여 이러한 차이를 줄이려는 시도이다.

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

키워드

참고문헌

  1. A. Fazio, et al., Intel Strata Flash Memory Technology Overview. http://www.intel.com/design/flash.
  2. M. Bauer et al. "A Multi-level Cell 32Mb Flash Memory.," In Proceedings of 42nd International Solid-State Circuits Conference, pp 132-133, Feb 1995.
  3. D. Elmhurst and M. Goldman, "A 1.8V 128 Mb 125 MHz Multilevel Cell Flash Memory With Flexible Read While Write," IEEE Journal of Solid State Circuits, 38(11):1929-1933, November 2003. https://doi.org/10.1109/JSSC.2003.818144
  4. M. Okhawa et al., "A 98mm2 3.3V, 64Mb Flash Memory with FN-NOR Type 4-Level Cell," In Proceedings of 43rd International Solid-State Circuits Conference, pp 36-37, February 1996.
  5. M. G. Mohammed and K. K. Saluja, "Flash Memory Disturbances: Modeling and Test," Proceedings of 19th VLSI Test Symposium, 2001, pp 218-224, April 2001.
  6. M. G. Mohammad, K. K. Saluja, and A. Yap, "Testing Flash Memories," In Proceedings of Thirteenth Int'l Conference on VLSI Design, pp 406-411, 2000.
  7. J. Yeh, C. et al, "Flash Memory Built-In Self Test Using March- Like Algorithms," In Proceedings of the First IEEE Intl. Workshop on Electronic Design, Test and Applications, pp 137-141, 2002.
  8. K. L. Cheng, J. C. Yeh, C. W. Wang, C.T. Huang, and C. W. Wu, "RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics," In Proceedings of 20th IEEE VLSI Test Symposium, pp 281-286, 2002.
  9. C. T. Huang, J. C. Yeh, Y. Y. Shih, R. F. Huang, and C. W. Wu, "On Test and Diagnostics of Flash Memories," In Proceedings of 13th Asian Test Symposium, pp 260-265, November 2004.
  10. C. L. Su, R. F. Huang, and C. W. Wu, "A Processor-Based Built-In Self-Repair Design for Embedded Memories," In Proceedings of 12th Asian Test Symposium, pp 366-371, November 2003.
  11. Y. Horng, J. Huang, and T. Chang, "March Test and On-Chip Test Circuit of Flash Memories," In Proceedings of 43rd Midwest Symposium on Circuits and Systems, volume 1, pp 128-131, August 2000.
  12. S. K. Chiu, J. C. Yeh, C. H. Huang, and C. W. Wu, "Diagonal Test and Diagnostic Schemes for Flash Memories," In Proceedings of International Test Conference, pp 37-46, 2002.
  13. Yu-Ying Hsiao, Chao-Hsun Chen, and Cheng-Wen Wu, "Built-In Self-Repair Schemes for Flash Memories", IEEE Transactions on computer-aided design of integrated circuits and systems, Vol. 29, No. 8, August 2010.
  14. Pavan P, Bez R, Olivo P, Zanoni E. "Flash memory cells-.an overview," Proc IEEE 1997;85(8):1248-71 https://doi.org/10.1109/5.622505
  15. Tei-Wei Kuo, Po-Chun Huang, Yuan-Hao Chang, Chia-Ling Ko, Chih-Wen Hsueh, "An efficient fault detection algorithm for NAND flash memory," Proc ACM SIGAPP Applied Computing Review, Vol 11, Issue 2, 2011.
  16. Advantech, Comparing SLC and MLC Flash Technologies and Structure, September, 2009.
  17. S. K. Chiu, J. C. Yeh, C. H. Huang, and C. W. Wu, "Diagonal Test and Diagnostic Schemes for Flash Memories," In Proceedings of International Test Conference, pp 37-46, 2002.