The Journal of the Korea Contents Association (한국콘텐츠학회논문지)

The Korea Contents Association (한국콘텐츠학회)
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Multiaccess Memory System supporting Local Buffer Memory System to Processing Elements

처리기에 지역 버퍼 메모리 시스템을 지원하는 다중접근기억장치

  • 이형 (대전보건대학교 방송제작과)
  • Received : 2011.08.09
  • Accepted : 2011.11.11
  • Published : 2012.01.28
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Abstract

A memory system with the linear skewing scheme has been regarded as one of suitable memory systems for a single instruction, multiple data (SIMD) architecture. The memory system supports simultaneous access n data to m memory modules within various access types with a constant interval in an arbitrary position in two dimensional data array of $M{\times}N$. Although $m{\times}cells$ memory cells are physically required to support logical two dimensional $M{\times}N$ array of data by means of the memory system, at least (m-n)${\times}cells$ memory cells remain in disuse, where cells is (M-1)/q+(N-1)/$p{\times}{\lceil}M/q{\rceil}+1$. On keeping functionalities the memory system supports, $(n{\times}t){\times}N/p$ out of a number of unused memory cells, where t>0, being used as local buffer memories for n processing elements is proposed in this paper.

선형 비틀림 구조를 갖는 메모리 시스템은 SIMD 구조에 적합한 메모리 시스템으로써, 2차원 데이터 배열인 $M{\times}N$에서 임의의 위치로부터 임의의 간격을 갖고 다양한 접근형태들로, m개의 메모리 모듈들에서 n개의 데이터를 동시에 접근할 수 있다. 그러나 이러한 메모리 시스템은 논리적인 2차원 $M{\times}N$ 데이터 배열을 지원하기 위해 $m{\times}cells$의 물리적인 메모리 용량이 필요하지만, 적어도 (m-n)${\times}cells$만큼의 메모리 셀은 사용되지 않는다. 여기서 cells는 (M-1)/q+(N-1)/$p{\times}{\lceil}M/q{\rceil}+1$이다. 본 논문에서는 이러한 메모리 시스템의 모든 기능들을 수용하면서 t>0인 조건 하에 사용되지 않는 메모리 셀들 중 $(n{\times}t){\times}N/p$ 만큼을 n개의 처리기들에 지역 버퍼 메모리로 제공할 수 있는 방법을 제안한다.

Keywords

References

  1. D. B. Kirk and Wen-mei W. Hwu, Programming Massively Parallel Processors: A Hands-on Approach, Morgan Kaufmann Pub., 2010.
  2. T. G. Mattson, B. A. Sanders, and B. L. Massingill, Patterns for Parallel Programming, Addison-wesley Pub., 2005.
  3. D. T. Harper III. "Block, Multistride Vector, and FFT Accesses in Parallel Memory System," IEEE Trans. Parallel and Distributed Systems, Vol.2, No.1, pp.43-51, 1991(1). https://doi.org/10.1109/71.80188
  4. R. Raghavan and J. P. Hayes, "On Randomlu Interleaved Memories," Proc. Supercomputing '90, pp.49-58, 1990.
  5. N. B. MacDonald, "An Overview of SIMD Parallel System: AMT DAP, Thinking Machines CM-200, and MasPar MP-1," Proc. Workshop Parallel Computing, 1992(4).
  6. K. Kim and V. K. P Kumar, "Perfect Latin Squares and Parallel Array Access," Pro. Int'l Symp. Computer Architecture, pp.372-379, 1989.
  7. D. T. Harper III. "A Multiacess Frame Buffer Architecture," IEEE Trans. Computers, Vol.43, pp.618-622, 1994(5). https://doi.org/10.1109/12.280810
  8. P. Budnik and D. J. Kuck, "The Organization and USe of Parallel Memories," IEEE Trans. Computers, Vol.20, No.12, pp.1566-1569, 1971(12). https://doi.org/10.1109/T-C.1971.223171
  9. D. H. Lawire, "Access and Alignment of Data in an Array Processor," IEEE Trans. Computers, Vol.24, No.12, pp.1145-1155, 1975(12). https://doi.org/10.1109/T-C.1975.224157
  10. D. C. Van Voorhis and T.H.Morrin, "Memory System for Image Processing," IEEE Trans. Computers, Vol.27, No.2, pp.113-125, 1978(2). https://doi.org/10.1109/TC.1978.1675045
  11. D. H. Lawrie and C. R. Vora, "The Prime Memory System for Array Access," IEEE Trans. Computers, Vol.31, No.5, pp.435-442, 1982(5). https://doi.org/10.1109/TC.1982.1676020
  12. J. W. Park, "An Efficient Buffer Memory System for Subarray Access," IEEE Trans. Parallel and Distributed Systems, Vol.12, No.3, pp.316-335, 2001(3). https://doi.org/10.1109/71.914779
  13. Eero Aho, Jarno Vanne, and T. D. Hamalainen, "Parallel Memory Architecture for Arbitrary Stride Access," In Proc. of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and System, pp.65-70, 2006(4).
  14. J. K. Tanskanen and T. Pitkanen, "Parallel Memory Architecture for TTA Processor," Proc. of the 7th Int. Conf. on Embedded Computer Sys.: Architecture Modelling, and Simulation," pp.273-283, 2007.
  15. Dionysios Reisis and Nikolaos Vlassopoulos, "Conflict-free Parallel Memory Accessing Techniques for FFT Architecture," IEEE Trans. on Circuits and Systems, Vol.55, No.11, pp.3438-3447, 2008(12). https://doi.org/10.1109/TCSI.2008.924889
  16. J. W. Park, "Multiaccess Memory System for Attached SIMD Computer," IEEE Trans. Computers, Vol.53, No.3, pp.1-14, 2004(3). https://doi.org/10.1109/TC.2004.1255787
  17. H. Lee and J. W. Park, "Parallel Processing System for Multi-Access Memory System," Proc. World Multi-conference of Systematics, Cybernetics, and Informatics, pp.561-565, 2000.
  18. H. Lee, H. K. Cho, D. S. You, and J. W. Park, "MAMS-PP4: Multi-Access Memory System used to improve the processing speed of Visual Media Applications in a Parallel Processing System," IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, Vol.E87-A, No.11, pp.2852-2858, 2004(11).