Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A Fractional-N PLL with Phase Difference-to-Voltage Converter

위상차 전압 변환기를 이용한 Fractional-N 위상고정루프

  • 이상기 (부경대학교 일반대학원 전자공학과) ;
  • 최영식 (부경대학교 전자공학과)
  • Received : 2012.06.11
  • Accepted : 2012.06.18
  • Published : 2012.12.31
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Abstract

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

본 논문에서는 기존의 fractional-N 위상고정루프의 가장 큰 문제점인 fractional 스퍼를 억제하기 위해 위상차-전압 변환기(Phase Difference-to-Voltage Converter : PDVC)를 도입하였다. PDVC는 위상주파수 검출기 출력 신호의 위상차에 따라 전하펌프의 전류량을 조절한다. 제안한 구조는 위상 주파수 검출기(phase frequency detector) 신호들의 위상차가 커지면 전하펌프(charge pump) 전류를 감소시켜 fractional 스퍼를 줄일 수 있는 구조이다. 회로는 1.8V $0.18{\mu}m$ CMOS 공정의 파라미터를 이용하여 HSPICE로 시뮬레이션을 수행하고 회로의 동작을 검증하였다.

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References

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