JSTS:Journal of Semiconductor Technology and Science

  • 제12권4호
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  • Pages.388-396
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  • 2012
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

  • Cho, Kyuik (Dongguk Univ.-Seoul, Dept. of Semiconductor Science) ;
  • Kim, Daeyun (Dongguk Univ.-Seoul, Dept. of Semiconductor Science) ;
  • Song, Minkyu (Dongguk Univ.-Seoul, Dept. of Semiconductor Science)
  • 투고 : 2012.01.26
  • 발행 : 2012.12.31
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초록

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

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참고문헌

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피인용 문헌

  1. Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC vol.14, pp.2, 2014, https://doi.org/10.5573/JSTS.2014.14.2.246
  2. A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier vol.15, pp.3, 2015, https://doi.org/10.3390/s150305081