전기전자학회논문지 (Journal of IKEEE)

  • 제15권2호
  • /
  • Pages.113-121
  • /
  • 2011
  • /
  • 1226-7244(pISSN)
  • /
  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지
DOI QR코드

DOI QR Code

디스플레이 포트를 위한 고속 보조 채널 설계

Fast Auxiliary Channel Design for Display Port

  • Jin, Hyun-Bae (School of Electronics Engineering, Inha University) ;
  • Moon, Yong-Hwan (School of Electronics Engineering, Inha University) ;
  • Jang, Ji-Hoon (School of Electronics Engineering, Inha University) ;
  • Kim, Tae-Ho (School of Electronics Engineering, Inha University) ;
  • Song, Byung-Cheol (School of Electronics Engineering, Inha University) ;
  • Kang, Jin-Ku (School of Electronics Engineering, Inha University)
  • 투고 : 2011.06.01
  • 발행 : 2011.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 디스플레이포트의 보조채널에서 고속 데이터 전송을 할 수 있는 고속 양방향 보조 채널을 구성하기 위한 새로운 송 수신기 구조를 제안하고 적용에 대해 서술하였다. 제안된 고속 보조 채널은 저속 전송에서 맨체스터 인코딩을 사용하여 1Mbps대역폭을, 고속 전송에서 8B/10B인코딩 방식을 사용하여 720Mbps의 대역폭을 지원한다. 맨체스터 전송을 사용하여 고속 보조채널 및 메인링크의 링크 서비스 및 디바이스 서비스를 위한 저속 보조채널 블록을 제안하고, 8B/10B인코딩 방식을 통하여 보조채널을 통한 고속 데이터 전송을 위한 블록을 제안한다. 또한 데이터 패킷 구조와 데이터 전송방식에 대하여 정의하였다. 설계된 시스템은 Verilog HDL로 설계 되었으며, 고속 보조채널 송 수신기는 Xilinx Vertex4 FPGA을 사용하여 합성한 결과 7,648개의 LUTs와 6,020개의 registers를 사용 하였으며, 최대 동작 속도는 203MHz의 성능을 확인 하였다.

This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel transmitter and receiver are implemented with 7,648 LUTs and 6,020 slice register synthesized in Xilinx Vertex4 FPGA and can be operated at 72MHz to support 720Mbps.

키워드

참고문헌

  1. Hitachi, Ltd., Matsushita Electric Industrial Co., Ltd.Philips Consumer Electronics, International B.V., Silicon Image, Inc., Sony Corporation, Thomson Inc., Toshiba Corporation, "High-Definition Multimedia Interface Specification," Version 1.3, June 22, 2006
  2. Digital Display Working Group, "Digital Visual Interface DVI," Revision 1.0, April 1999
  3. National Semiconductor, "LVDS owner's manual, " 3rd Edition, Spring 2004
  4. Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, NEC, Philips, "Universal Serial Bus Specification," Revision 2.0, April 27, 2000
  5. VESA, VESA DispalyPort Standard, Version 1, Revision 1a, January 11, 2008
  6. VESA, VESA DisplayPort Standard, Version 1, Revision 2, January 5, 2010
  7. VESA, DisplayPort Link Layer Compliance Test Standard, Version 1.0, September 14, 2007
  8. Yoo-woo Kim, Seong-bok Cha, and Jin-Ku, "A Design of DisplayPort Link Layer," International SoC Design Conference, pp. 45-48, November, 2008
  9. Seong-bok Cha, Yong-woo Kim, and Jin-Ku Kang, "A Design of DisplayPort AUX Channel," SoC Conference, Jeonju, Korea, May 2009
  10. A. X. widmer, "A DC-balanced, Partitioned-Block, 8B/10B Transmission Code," IBM J. Res. Develop, vol.27 pp. 440-451, September 1983 https://doi.org/10.1147/rd.275.0440
  11. ARM, AMBA Specification, Rev 2.0, 1999
  12. A. Bystrov, D.J .Kinniment and A. Yakovlev, "Priority Arbiters", in Proc. IEEE 6th international Symp. ASYNC, pp.128-137, April. 2000
  13. Mary K. Vernon and U. Manber, "Distributed Round-Robin and First-come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration", The ACM 15th Annual International Symposium on Computer Architecture, 1988
  14. Y. Xu, L. Li, Ming-lun Gao, B.Zhand, Zhao-yu Jiand, Gao-ming Du and W.Zhang, "An Adaptive Dynamic Arbiter for Multi-Processor SoC", Solid-State and Integrated Circuit Technology International Conf., pp.1993-1996, 2006
  15. S.Shimizu, T.Matsuoka, and K.Taniguchi, "Parallel bus systems using code-division multiple access technique",in Proc. IEEE Int. Symp. Circuits Syst., pp.II-240-II-243, 2003
  16. K. Lahiri, A. Raghunathan and G. Lakshminarayana, "The LOTTERY BUS On-Chip Communication Architecture",IEEE Trans. VLSI Systems, vol.14, no.6, 2006
  17. K. Kim, S. Lee, K. Lee, and H. Yoo, "an arbitration look-ahead scheme for reducing end-to-end latency in networks on chip,"IEEE Circuits and Systems, pp.2357-360, 2005