전기전자학회논문지 (Journal of IKEEE)

  • 제15권1호
  • /
  • Pages.37-42
  • /
  • 2011
  • /
  • 1226-7244(pISSN)
  • /
  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지
DOI QR코드

DOI QR Code

고내압 BCD 소자의 제작 및 전기적 특성에 관한 연구

A Study on the Fabrication and Electrical Characteristics of High-Voltage BCD Devices

  • 김광수 (서강대학교 서강미래기술원) ;
  • 구용서 (단국대학교 전자전기공학과)
  • Kim, Kwang-Soo (Sogang Institute of Advanced Technology, Sogang University) ;
  • Koo, Yong-Seo (School of Electrical and Electronics Engineering, Dankook University)
  • 투고 : 2011.03.05
  • 발행 : 2011.03.31
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 0.35 um BCD 공정을 통한 고내압 BCD 소자와 새로운 구조의 BCD 소자를 제작하여 전기적 특성을 분석하였다. 20 V급 BJT 소자, 30/60 V급 HV-CMOS, 40/60 V급 LDMOS 소자의 전기적 특성을 분석하고, 동일 공정을 통해 높은 전류 이득을 갖는 수직/수평형 NPN BJT와 고내압 특성의 LIGBT 소자를 제안하였다. 제안된 수직/수평형 NPN BJT의 항복전압은 15 V, 전류이득은 100으로 측정되었으며, 고내압 특성의 LIGBT의 항복전압은 195 V, 문턱전압은 1.5 V, Vce,sat은 1.65 V로 측정 되었다.

In this paper, the high-voltage novel devices have been fabricated by 0.35 um BCD (Bipolar-CMOS-DMOS) process. Electrical characteristics of 20 V level BJT device, 30/60 V HV-CMOS, and 40/60 V LDMOS are analyzed. Also, the vertical/lateral BJT with the high-current gain and LIGBT with the high-voltage are proposed. In the experimental results, vertical/lateral BJT has breakdown voltage of 15 V and current gain of 100. The proposed LIGBT with the high-voltage has breakdown voltage of 195 V, threshold voltage of 1.5 V, and Vce, sat of 1.65 V.

키워드

참고문헌

  1. D. Riccardi et al., "BCD8 form 7V to 70V: a new 0.18 um technology platform to address the evolution of applications towards smart power ICs with high logic contents," ISPSD, pp.73-76, 2007
  2. A. Moscatelli et al., "LDMOS implementation in a 0.35 um BCD technology(BCD6)," ISPSD, pp.419-422, 2004
  3. A. Andreini, C. Contiero, and P.Galbiati, "A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts," IEEE Trans. Electron Devices, Vol.33, pp.2025-2030, 1996
  4. Chen Zhiyong, Huang Qiyu, Gong Dawei, "Introduction of BCD Process," Semiconductor Technology, Vol.31, No.9, pp.641-644, 2006
  5. Udrea, F., "Advanced 3D RESURF devices for power integrated circuits," Semiconductor Conference, CAS 2002 Proceedings. International, Vol.2, pp.229-238, 2002
  6. J. Appels, H. Vaes, J. Verhoeven, "HV thin-layer devices (Resurf devices)," IEDM, pp.238-241, 1979
  7. J. Appels, M. collet, P. Hart, H. Vaes, J. Verhoeven, "Thin-layer HV-devices," Philips Journal Research.35, pp.1-13, 1980
  8. Adriaan W., Ludikhuize, "A Review of RESURF Technology," ISPSD, pp.11-18, 2000