DOI QR코드

DOI QR Code

High Speep/High-Precision Chip Joining Using Self-Assembly Technology for Three-Dimensional Integrated Circuits

삼차원적층형 집적회로 구현을 위한 자기조직화정합기술을 이용한 고속.고정밀 접합기술


Abstract

본 논문에서는 액체의 표면장력을 이용하여 복수의 KGD 들을 웨이퍼 상태에서 일괄접합함으로써, 높은 수율의 삼차원적층칩을 빠른 생산성으로 제작할 수 있는, 고속 고정밀 접합기술인 자기조직화정합 (Selfassembly) 기술에 대해 소개를 하였다. 본 연구실에서 개발한 self-assembly 기술을 적용하여 5mm 각(角) 크기의 칩 500개를 1초 이내에 평균 $0.5{\mu}m$ 정도의 높은 정밀도로 8인치 웨이퍼상에 일괄접합시키는데 성공하였다. Self-assembly 기술에 의한 삼차원 칩 적층방식은, 기존의 pick-and-place 적층방식에서 높은 정밀도의 접합특성을 확보하는데 필요한 공정시간을 혁신적으로 단축하는 것이 가능하고, 웨이퍼 레벨에서 복수의 KGD 들을 일괄접합하는 것이 가능하므로, 향후 TSV 기술의 양산화를 실현하는데 적합한 고속 고정밀 접합 기술로서 기대가 크다. 현재 본 연구실에서는 두께가 $50{\mu}m$ 이하의 얇은 LSI 칩 및 메탈범프가 형성된 LSI 칩 등을 이용하여, self-assembly 기술에 의한 삼차원 적층형 집적회로 구현을 위한 접합기술을 개발 중에 있다.

Keywords

References

  1. T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, "Three dimensional ICs, having four stacked active device layers," IEEE International Electron Devices Meeting (IEDM), 837 (1989) https://doi.org/10.1109/IEDM.1989.74183
  2. M. Koyanagi, H. Kurino, K-W. Lee, K. Sakuma, N. Miyakawa, H. Itani, "Future System-on-Silicon LSI chips," IEEE MICRO, 18 (4), 17 (1998) https://doi.org/10.1109/40.710867
  3. S.J. Souri, K. Banerjee, A. Mehrotra, and K.C. Saraswat, "Multiple Si layer ICs: Motivation, performance analysis, and design implications," in Proc. 37th ACM Design Automation Conf., 873 (2000)
  4. P. Ramm, D. Bonfert, H. Gieser, J. Haufe, F. Iberl, A. Klumpp, A. Kux, R. Wieland, "Interchip via technology for vertical system integration," Proc. IEEE Int. Interconnect Technology Conf. (IITC), 160 (2001) https://doi.org/10.1109/IITC.2001.930046
  5. K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," PROCEEDING OFTHE IEEE, 89 (5), 602 (2002) https://doi.org/10.1109/5.929647
  6. M. Koyanagi, T. Fukushima, and T. Tanaka, "High-density through silicon vias for 3D-LSIs," Proc. IEEE 97 (1), 49 (2006)
  7. K.W Lee, "The next generation package technology for higher performance and smaller systems", in Proc. 3rd Int. Conf. 3D Architect. Semicond. Integr. Packag., (2006)
  8. J.-Q. Lu, K. Rose, and S. Vitkavage, "3D Integration: Why, what, who, when? ", Future Fab Int., 23, 25 (2007)
  9. F. Carson, "3D SiP development and trends", in 3D packag. Workshop IMAPS Int. Conf. Exhib. Device Packag. Conf., (2007)
  10. Min-Seung Yoon, "Introduction of TSV (Through Silicon Via) Technology", J. Microelectron. Packag. Soc., 16 (1), 1 (2009)
  11. T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New Three-Dimensional Integration Technology Using Self-Assembly Technique", IEEE International Electron Devices Meeting (IEDM), 359 (2005)
  12. T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koyanagi, "New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique", IEEE International Electron Devices Meeting (IEDM), 985 (2007) https://doi.org/10.1109/IEDM.2007.4419119
  13. K-W Lee, and M. Koyanagi, "Novel Interconnection Technology for Heterogeneous Integration of MEMSLSI Multi-Chip Module", Journal of Microsystem and Technology, 16 (3), 441 (2010) https://doi.org/10.1007/s00542-009-0941-z
  14. K-W Lee, A. Noriki, K. Kiyoyama, S. Kanno, W-C Jeong, T. Fukushima, T. Tanaka, M. Koyanagi, "3D Heterogeneous Opto-Electronic Integration Technology for System-on-Silicon (SOS)", IEEE International Electron Devices Meeting (IEDM), 531 (2009)
  15. Mitsumasa Koyanagi, Takafumi Fukushima, Kang-Wook Lee, and Tetsu Tanaka, "Super-chip Aiming Ultimate Heterogeneous Integration", IEICE, 93 (11), 918 (2010).
  16. M. Koyanagi, "Roadblocks in Achieving Three-Dimensional LSI," Proc. 8th Symposium on Future Electron Devices, 50 (1989)
  17. T. Matsumoto, M. Satoh, K. Sakuma, H. Kurino, N. Miyakawa, H. Itani, and M. Koyanagi, "New three dimensional wafer bonding technology using the adhesive injection method", Jpn. J. Appl., 37 (3B), 1217 (1998) https://doi.org/10.1143/JJAP.37.1217
  18. Y. Igarashi, T. Morooka, Y. Yamada, T. Nakamura, K.W.Lee, K.T. Park, H. Itani, and M. Koyanagi, "Filling of tungsten into deep trench using time-modulation CVD method", Proc. Int. Conf. Solid State Devices and Mater., 34 (2001)
  19. M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, "Threedimensional integration technology based on wafer bonding with vertical buried interconnections", IEEE Trans. Electron Devices, 53 (11), 2799 (2006) https://doi.org/10.1109/TED.2006.884079
  20. T. Matsumoto, Y. Kudoh, M. Tanara, K.H. Yu, N. Miyakawa, H. Itani, T. Ichikizaki, H. Tsukamoto, and M. Koyanagi, "Three-dimensional integration technology based on wafer bonding technique using micro-bumps", Proc. Int. Conf. Solid State Devices and Mater., 1073 (1995)
  21. M. Motoyoshi, K. Kamibayashi, M. Koyanagi, and M. Bonkohara, "Current and future 3-dimensional LSI technologies", Tech. Dig. 3D System Integration Conf., 8.1 (2007)
  22. Y. Ohara, A. Noriki, K. Sakuma, K.W. Lee, J. Bea, F. Yamada, T. Fukushima, T. Tanaka, and M. Koyanagi, "10um fine pitch Cu/Sn micro-bumps for 3-D super-chip stack", Tech. Dig. 3D System Integration Conf., (2009)
  23. T. Matsumoto, M. Satoh, K. Sakuma, Hu. Kurino, N. Miyakawa, H. Itani, T. Ichikizaki, H. Tsukamoto, and M. Koyanagi, "New three-dimensional wafer bonding technology using adhesive injection method", Proc. Int. Conf. Solid State Devices and Mater., 460 (1997)
  24. H. Kurino, K-W. Lee, K. Sakuma, T. Nakamura, M. Koyanagi, "A New Wafer Scale Chip-on-Chip (W-COC) Packaging Technology using Adhesive Injection Method", Jpn.J.Appl.Phys., 38, 2406 (1999) https://doi.org/10.1143/JJAP.38.2406
  25. H. Kurino, K-W. Lee, T. Nakamura, K. Sakuma, K-T. Park, N. Miyakawa, H. Shimatzu, K. Inamura, M. Koyanagi, "Intelligent Image Sensor Chip with Three Dimensional Structure", IEEE International Electron Devices Meeting (IEDM), 879 (1999)
  26. K-W. Lee, T. Nakamura, T. Ono, Y. Yamada, H. Hashimoto, K-T. Park, H. Kurino, M. Koyanagi, "Three Dimensional Shared Memory Fabricated using Wafer Stacking Technology", IEEE International Electron Devices Meeting (IEDM), 165 (2000)
  27. M. Koyanagi, Y. Nakagawa, K-W. Lee, T. Nakamura, Y. Yamada, K. Inamura, K-T. Park, H. Kurino, "Neuromorphic Vision Chip Fabricated using Three-Dimensional Integration Technology", IEEE Int. Solid State Circuits Conference (ISSCC), 270 (2001)
  28. T. Ono, T. Mizukusa, T. Nakamura, Y. Yamada, Y. Igarashi, T. Morooka, H. Kurino, and M. Koyanagi, "Three-dimensional processor system fabricated by wafer stacking technology", Pro. Int. Symp. Low-Power and High-Speed Chips (COOL Chips), 186 (2002)
  29. K. Hozawa, H. Miyazaki, and J. Yugami, "True influence of wafer-backside copper contamination during the back-end process on device characteristics," IEEE International Electron Devices Meeting (IEDM), 737 (2002)
  30. J.C. Bae, K.W. Lee, T. Fukushima, T. Tanaka, and M. Koyanagi, "Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient Capacitance Measurement", IEEE Electron Device Letters, (in press, January 2011)
  31. J.-C. Bea, K.-W. Lee, M. Murugesan, T. Fukushima, T. Tanaka and M. Koyanagi, "Evaluation of Copper Diffusion in Thinned Wafer with Extrinsic Gettering for 3D-LSI by Capacitance-Time (C-t) measurement", Int. Conf. On. Solid State Devices and Materials (SSDM), Sep. (2010)
  32. M. Murugesan, J-C. Bea, H. Kino, Y. Ohara, M. Kojima, A. Noriki, K-W. Lee, K. Kiyoyama, T. Fukushima, H. Nohira, T. Hattori, E. Ikenaga, T. Tanaka, M. Koyanagi, "Impact of Remnant Stress/Strain and Metal Contamination in Extremely Thin (-10 ${\mu}m$) Si Wafers in the 3D IntegrationTechnology", IEEE International Electron Devices Meeting (IEDM), 361 (2009)
  33. Sung-Hwan Hwang, Byoung-Joon Kim, Sung-Yup Jung, Ho-Young Lee and Young-Chang Joo, "Thermo-Mechanical Analysis of Though-silicon-via in 3D Packaging", J. Microelectron. Packag. Soc., 17 (1), 69 (2010)
  34. Eun-Kyung Kim, "Assessment of ultra-thin Si wafer thickness in 3D wafer stacking", Microelectronics Reliability, 50, 195 (2010) https://doi.org/10.1016/j.microrel.2009.10.002
  35. T. Fukushima, E. Iwata, T. Konno, J.-C. Bea, K.-W. Lee, T. Tanaka, and M. Koyanagi, "Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits", APPLIED PHYSICS LETTERS, 96 (15), 154105 (2010)
  36. Eiji Iwata, Takafumi Fukushima, Ohara Yuki, Kang-Wook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi, "High-Precision Chip Alignment Using Self-Assembly Technology for Three-Dimensional Integrated Circuit Applications", IEICE, 93-C (11), 493 (2010)
  37. M. Koyanagi, T. Fukushima, K.W. Lee, T. Tanaka, "3D Integration Technology and Heterogeneous Integration", IEICE, (in press, 2011)