Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of 10-Gb/s Adaptive Decision Feedback Equalizer with On-Chip Eye-Opening Monitoring

온 칩 아이 오프닝 모니터링을 탑재한 10Gb/s 적응형 Decision Feedback Equalizer 설계

  • Seong, Chang-Kyung (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Rhim, Jin-Soo (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Choi, Woo-Young (Department of Electrical and Electronic Engineering, Yonsei University)
  • 성창경 (연세대학교 전기전자공학과) ;
  • 임진수 (연세대학교 전기전자공학과) ;
  • 최우영 (연세대학교 전기전자공학과)
  • Received : 2010.11.16
  • Accepted : 2010.12.29
  • Published : 2011.01.25
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Abstract

With the increasing demand for high-speed transmission systems, adaptive equalizers have been widely used in receivers to overcome the limited bandwidth of channels. In order to reduce the cost for testing high-speed receiver chips, on-chip eye-opening monitoring (EOM) technique which measures the eye-opening of data waveform inside the chip can be employed. In this paper, a 10-Gb/s adaptive 2-tap look-ahead decision feedback equalizer (DFE) with EOM function is proposed. The proposed EOM circuit can be applied to look-ahead DFEs while existing EOM techniques cannot. The magnitudes of the post-cursors are measured by monitoring the eye of received signal, and coefficients of DFE are calculated using them by proposed adaptation algorithm. The circuit designed in 90nm CMOS technology and the algorithm are verified with post-layout simulation. The DFE core occupies $110{\times}95{\mu}m^2$ and consumes 11mW in 1.2V supply voltage.

고속 전송 시스템에 대한 수요가 증가함에 따라 채널의 제한된 대역폭을 극복하기 위한 적응형 등화기가 수신기에 널리 사용되고 있다. 수신기 칩의 테스트 비용을 절감하기 위하여 칩 내부에서 데이터의 아이 열림 정도를 측정할 수 있는 온 칩 eye-opening monitoring (EOM) 기술이 사용될 수 있다. 본 논문에서는 EOM 기능을 탑재한 10Gb/s 적응형 2탭 look-ahead decision feedback equalizer (DFE)를 제안한다. 제안된 EOM 회로는 기존의 방식과 달리 look-ahead DFE의 등화 신호를 모니터링 할 수 있다. 수신 신호의 아이로부터 포스트 커서의 크기를 측정한 후, 등화 계수가 제안된 알고리즘에 의하여 계산된다. 제안된 회로는 90nm CMOS 공정에 설계되었으며 알고리즘과 함께 post-layout 시뮬레이션을 통하여 동작을 검증하였다. DFE 코어논 $110{\times}95{\mu}m^2$의 면적을 가지고 1.2V의 전원에서 11mW를 소모한다.

Keywords

References

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