Multi -Core Transactional Memory for High Contention Parallel Processing

집중 충돌 병렬 처리를 위한 효율적인 다중 코어 트랜잭셔널 메모리

  • Kim, Seung-Hun (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Sun-Woo (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Ro, Won-Woo (Department of Electrical and Electronic Engineering, Yonsei University)
  • 김승훈 (연세대학교 전기전자공학과) ;
  • 김선우 (연세대학교 전기전자공학과) ;
  • 노원우 (연세대학교 전기전자공학과)
  • Received : 2010.08.25
  • Accepted : 2010.12.23
  • Published : 2011.01.25

Abstract

The importance of parallel programming seriously emerges ever since the modern microprocessor architecture has been shifted to the multi-core system. Transactional Memory has been proposed to address synchronization which is usually implemented by using locks. However, the lock based synchronization method reduces the parallelism and has the possibility of causing deadlock. In this paper, we propose an efficient method to utilize transactional memory for the situation which has high contention. The proposed idea is based on the theoretical analysis and it is verified with simulation results. The simulation environment has been implemented using HTM(Hardware Transactional Memory) systems. We also propose a model of the dining philosopher problem to discuss the efficient resource management using the transactional memory technique.

다중 코어 프로세서의 보급과 더불어 이를 효율적으로 활용하기 위한 병렬 프로그래밍의 중요성은 나날이 강조되고 있다. 트랜잭셔널 메모리는 병렬 프로그래밍의 핵심적인 요소인 동기화(Synchronization)를 위해 제안된 구조로서 lock을 사용한 동기화로 인해 발생하는 병렬성 저하, deadlock 등의 문제를 극복할 수 있다. 본 논문은 높은 수준의 contention 상황에 따른 효율적인 트랜잭셔널 메모리의 구조에 대한 이론적인 분석을 제시하며 시뮬레이션을 통해 분석의 타당성을 확인한다. 시뮬레이션 환경은 하드웨어 트랜잭셔널 메모리 (Hardware Transactional Memory) 시스템으로 구성되었으며 이론의 검증을 위해 STAMP 벤치마크와 높은 contention을 유발하는 프로그램을 시뮬레이션 하였다. 또한 트랜잭셔널 메모리를 적용한 dining philosopher problem의 모델링을 통해 효율적인 자원 할당 방안에 있어 lazy 데이터 관리 정책이 유리함을 보였다.

Keywords

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