Journal of Information Processing Systems

  • 제7권1호
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  • Pages.85-92
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  • 2011
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  • 1976-913X(pISSN)
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  • 2092-805X(eISSN)
한국정보처리학회 (Korea Information Processing Society)
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Effective Partitioning of Static Global Buses for Small Processor Arrays

  • Matsumae, Susumu (Dept. of Information Science, Graduate School of Science and Engineering, Saga University)
  • 투고 : 2010.10.01
  • 심사 : 2011.02.22
  • 발행 : 2011.03.31
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초록

This paper shows an effective partitioning of static global row/column buses for tightly coupled 2D mesh-connected small processor arrays ("mesh", for short). With additional O(n/m (n/m + log m)) time slowdown, it enables the mesh of size $m{\times}m$ with static row/column buses to simulate the mesh of the larger size $n{\times}n$ with reconfigurable row/column buses ($m{\leq}n$). This means that if a problem can be solved in O(T) time by the mesh of size $n{\times}n$ with reconfigurable buses, then the same problem can be solved in O(Tn/m (n/m + log m)) time on the mesh of a smaller size $m{\times}m$ without a reconfigurable function. This time-cost is optimal when the relation $n{\geq}m$ log m holds (e.g., m = $n^{1-\varepsilon}$ for $\varepsilon$ > 0).

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참고문헌

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