대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

선택적으로 클럭 신호를 입력하는 저 전력 전류구동 디지털-아날로그 변환기

A Low Power Current-Steering DAC Selecting Clock Enable Signal

  • 양병도 (충북대학교 전자정보대학) ;
  • 민제중 (충북대학교 전자정보대학)
  • Yang, Byung-Do (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Min, Jae-Joong (College of Electrical and Computer Engineering, Chungbuk National University)
  • 투고 : 2011.06.30
  • 심사 : 2011.10.10
  • 발행 : 2011.10.25
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초록

본 논문에서는 선택적으로 클럭 신호를 입력하는 저 전력 전류구동 10비트 D/A 변환기 회로를 제안하였다. 제안된 DAC에서는 데이터가 변하지 않는 전류원 셀에 클럭 신호를 제한하여 클럭 전력 소모를 줄였다. 제안된 DAC는 1.2V 0.13${\mu}m$ CMOS 공정을 사용하여 제작되었으며, DAC 칩 면적은 0.21$mm^2$였다. 200MHz 샘플링 주파수와 1MHz 입력 신호 주파수에서, 제안된 DAC의 전력 소모량은 4.46mW였다. 클럭 신호에서 소모되는 전력은 입력 주파수가 1.25MHz와 10MHz일 때 각각 30.9%와 36.2%로 감소되었다. 측정된 SFDR은 입력주파수가 1MHz와 50MHz일 때 각각 72.8dB와 56.1dB였다.

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

키워드

참고문헌

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