DOI QR코드

DOI QR Code

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

  • 투고 : 2011.10.21
  • 발행 : 2011.12.31

초록

A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

키워드

참고문헌

  1. H. Xie, X. Wang, L. Lin, H. Tang, Q. Fang, H. Zhao, S. Wang, F. Yao, A. Wang, Y. Zhou, B. Qin, "A 52- mW 3.1-10.6-GHz Fully Integrated Correlator for IR-UWB Transceivers in 0.18m CMOS," IEEE Trans. Industrial Electronics, Vol.57, No.5, pp.1546 -1554, May, 2010. https://doi.org/10.1109/TIE.2009.2031670
  2. S.M. Louwsma, E.J.M. van Tuijl., M. Vertregt, B. Nauta, "A Time-Interleaved Track & hold in 0.13 $\mu m$ CMOS sub-sampling a 4 GHz signal with 43 dB SNDR," in Proc. IEEE Custom Integrated Circuits Conf.(CICC), pp.329-332, 16-19 Sep., 2007.
  3. T. Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata , H. Okada, "4-Gb/s track and hold circuit using parasitic capacitance canceller," Eur. Solid- State Circuits Conf.(ESSCIRC), pp.347- 350, 21-23 Sep., 2004.
  4. M. Okushima, J. Borremans, D. Linten, G. Groeseneken, "A DC-to-22 GHz 8.4mW compact dual-feedback wideband LNA in 90 nm digital CMOS," in Proc. IEEE Radio Frequency Integrated Circuits(RFIC) Symp., pp.295-298, 7-9 Jun., 2009.
  5. J. Borremans, P. Wambacq, C. Soens, Y. Rolain, and M. Kuijk, "Low-area active-feedback lownoise amplifier design in scaled digital CMOS," IEEE J. Solid-State Circuits, Vol.43, No.11, pp.2422-2432, Nov., 2008. https://doi.org/10.1109/JSSC.2008.2005434
  6. J. Choi, S. Seo, H. Moon, I. Nam, "A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 $\mu m$ CMOS," IEEE J. Semiconductor Technology and Science, Vol.11, No.3, Mar., 2011.
  7. D. Zito, D. Pepe, M. Mincica, F. Zito, "A 90 nm CMOS SoC UWB pulse radar for respiratory rate monitoring," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.40-41, 20-24 Feb., 2011.