대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

고주파 집적회로를 위한 ESD 보호회로 설계

Design of ESD Protection Circuits for High-Frequency Integrated Circuits

  • 김석 (성균관대학교 정보통신공학부) ;
  • 권기원 (성균관대학교 정보통신공학부) ;
  • 전정훈 (성균관대학교 정보통신공학부)
  • Kim, Seok (School of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (School of Information & Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (School of Information & Communication Engineering, Sungkyunkwan University)
  • 투고 : 2010.06.01
  • 심사 : 2010.07.20
  • 발행 : 2010.08.25
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 수 GHz를 상회하는 동작 주파수를 갖는 RF집적회로와 고속 디지털 인터페이스를 위한 ESD 보호회로의 다양한 설계방법을 기술한다. 입/출력에 상당한 양의 기생 커패시턴스를 가지는 ESD 보호소자는 입/출력 임피던스 매칭에 영향을 주며, 이득, 잡음 등의 RF특성을 열화시킨다. 본 논문에서는 이와 같은 ESD 보호소자의 악영향에 대해 분석하고, 이를 감쇄시킬 수 있는 방안을 논한다. 또한 RF 특성과 ESD 내성 측정을 통해 RF/ESD 병합설계 방법을 기존의 RF ESD 보호소자의 설계방법과 비교, 분석한다.

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

키워드

참고문헌

  1. C. Duvvury, "ESD qualification changes for 45nm and beyond" Proc. IEDM, 2008, pp. 1-4.
  2. J. Li, K. Chatty, R. Gauthier, R. Mishra, and C. Russ, "Technology Scaling of Advanced Bulk CMOS On-Chip ESD Protection down to the 32nm Node" Proc. EOS/ESD Symp., 2009, pp. 1-7.
  3. S. Cao, T. W. Chen, S. G. Beebe, R and W. Dutton, "ESD Design Challenges and Strategies in Deeply-scaled Integrated Circuits" Proc. IEEE CICC, 2009, pp. 681-688.
  4. K. Bhatia and E. Rosenbaum, "Layout guidelines for optimized ESD protection diodes" Proc. EOS/ESD Symp., 2007, pp. 19-27.
  5. O. Marichal, G. Wybo, B. Van Camp, P. Vanysacke and B. Keppens, "SCR based ESD protection in nanometer SOI technologies" Proc. EOS/ESD Symp., 2005, pp. 1-8.
  6. Y. Morishita and M. Okushima, "A low-leakage SCR design using trigger-PMOS modulations for ESD protection" Proc. EOS/ESD Symp., 2007, pp. 376-384.
  7. A. A.Salman, S. G. Beebe and M. M. Pelella, "Double well field effect diode: Lateral SCR-like device for ESD protection of I/Os in deep sub micron SOI" Proc. EOS/ESD Symp., 2007, pp. 1860-191.
  8. S. Galal and B. Razavi, "Broadband ESD protection circuits in CMOS technology," IEEE J. Solid-State Circuits, Vol. 38, No. 12, pp. 2334- 2340, Dec. 2003. https://doi.org/10.1109/JSSC.2003.818568
  9. W. Soldner, M. J. Kim, M. Streibl, H. Gossner, T. H. Lee and D. Schmitt-Landsiedel, "A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection" in Tech. Dig. ISSCC, pp. 550- 551, 2007.
  10. T. H. Lee, The design of CMOS radio-frequency integrated circuits: 2nd edition, cambridge, 2004.
  11. C. Ito, K. Banerjee and R. Dutton, "Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1444-1454, Aug. 2002. https://doi.org/10.1109/TED.2002.801257
  12. W. Soldner, M. Streibl, U. Hodel, M. Tiebout, H. Gossner, D. Schmitt-Landsiedel, J. Chun, C. Itoand R. W. Dutton, "RF ESD Protection Strategies: Codesign vs. Low-C Protection," Proc. EOS/ESD Symposium, Sept. 2005.
  13. S. Hyvonen, S. Joshi, and E. Rosenbaum, "Cancellation technique to provide ESD protection for multi-GHz RF inputs," Electronics Lett., vol. 39, no. 3, pp. 284-286, 2003. https://doi.org/10.1049/el:20030221
  14. S. Hyvonen, S. Joshi, and E. Rosenbaum, "Comprehensive ESD protection for RF inputs," Proc. EOS/ESD Symposium, pp. 188-194, Sept. 2003.
  15. B. Kleveland, T. J. Maloney, I. Morgan, L. Madden, T. H. Lee, and S. S. Wong, "Distributed ESD protection for high-speed integrated circuits," IEEE Electron Device Lett., vol. 21, pp. 390-392, Aug, 2000. https://doi.org/10.1109/55.852960
  16. I. Opris, "Bootstrapped pad protection structures," IEEE J. Solid-State Circuits, Vol. 33, No. 2, pp, 300-301, Feb. 1998. https://doi.org/10.1109/4.658635
  17. S. Galal and B. Razavi, "40-Gb/s amplifier and ESD protection circuit in 0.18-um CMOS technology," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2389-2396, Dec. 2004. https://doi.org/10.1109/JSSC.2004.835639
  18. D. Linten, S. Thijs, J. Borremans, M. Dehan, D. Tremouilles, M. Scholz, M. I. Natarajan, P. Wambacq and G. Groeseneken, "T-diodes-a novel plug-and-play wideband RF circuit ESD protection methodology," Proc. EOS/ESD Symposium, pp. 242-249, Sept. 2007.
  19. D. Leenaerts and R. Velghe, "Bond pad and ESD protection structure for 0.25 um/ 0.18 um RF-CMOS," Proc. ESSCIRC, pp. 569-572, Sept., 2003.
  20. B. Razavi, RF Micoroelectronics: Prentice Hall, A Simon & Schuster, 1998.
  21. K. Gong, H. Feng, R. Zhan and A. Wang, "A study of parasitic effects of ESD protection on RF ICs," IEEE Trans. Mircrowave Theory And Techniques, vol. 50, no. 1, pp. 393-402, Jan. 2002. https://doi.org/10.1109/22.981291
  22. A. Wang, H. G. Feng, R. Y. Zhan, G. Chen, and Q. Wu, "ESD protection design for RF integrated circuits: new challenges," Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 411-418, 2002.
  23. G. Gramegna, M. Paparo, P. G. Erratico, and P. D. Vita, "A sub-1-dB NF 2.3-kV ESD-protected 900-MHz CMOS LNA," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1010-1017, July, 2001. https://doi.org/10.1109/4.933455
  24. D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, "A 5-GHz fully integrated ESD-protected lownoise- amplifier in 90-nm RF CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1434- 1442, 2005. https://doi.org/10.1109/JSSC.2005.847490
  25. A. Wang, H. Feng, R. Zhan, H. Xie, G. Chen, Q. Wu, X. Guan, Z. Wang and C. Zhang, "A review on RF ESD protection design," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1304-1311, July 2005. https://doi.org/10.1109/TED.2005.850652
  26. V. Chandrasekhar and K. Mayaram, "Analysis of CMOS RF LNAs with ESD protection," Proc. Int. Sym. Circuits and Systems (ISCAS), pp. 799 -802, May, 2002.
  27. P. Leroux and M. Steyaert, "High-performance 5.2 GHz with on-chip inductor to provide ESD protection," Electron. Lett., vol. 37, no. 7, pp. 467 -469, 2001. https://doi.org/10.1049/el:20010271
  28. S. Joshi and E. Rosenbaum, "ESD protection for broadband ICs (DC-20 GHz and beyond)," Electronics Lett. Vol.39, no. 12, June, 2003.
  29. G. Gonzalez, Microwave transistor amplifiers: analysis and design, 2nd edition, Prentice Hall, NJ, 1997.
  30. M. Tiebout, "LNA design for a fully integrated CMOS single chip UMTS Tranceiver," Proc. ESSCIRC, pp. 835, 2002.
  31. S. Kim, S. Kim, G. Jung, K.-W. Kwon, and J. Chun, "Design of a reliable broadband I/O employing T-coil," Journal of Semiconductor Technology and Science, vol.9 no. 4, pp. 198- 204, Dec. 2009 https://doi.org/10.5573/JSTS.2009.9.4.198
  32. J. Chun, "ESD protection circuits for advanced CMOS technologies", Ph.D Dissertation, Stanford University, 2006.