Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of The 10bit 80MHz CMOS D/A Converter with Switching Noise Reduction Method

스위칭 잡음 감소기법을 이용한 10비트 80MHz CMOS D/A 변환기 설계

  • Received : 2009.12.29
  • Accepted : 2010.05.10
  • Published : 2010.06.25
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Abstract

This paper describes a 10 bit 80MHz CMOS D/A converter for wireless communication system. The proposed circuit in the paper is implemented with a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process. The architecture of the circuit consists of the 4bit LSB with binary decoder, and both the 3bit ULSB and the 3bit MSB with the thermometer decoder. The measurement results demonstrates SFDR of 60.42dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB of 8.75bit. INL and DNL have been measured to be ${\pm}$0.38LSB and ${\pm}$0.32LSB and glitch energy is measured to be 4.6$pV{\cdot}s$. Total power dissipation is 48mW at 80MHz(maximum sampling frequency) with a single power supply of 1.8V.

본 논문에서는 무선 통신 응용 시스템에 적합 하도록 10비트 80MHz 전류구동 방식의 D/A 변환기를 제안하였다. 제안한 회로는 $0.18{\mu}m$ CMOS n-well 1-poly 6-metal 공정을 이용하여 구현하였다. 10비트 중에서 LSB 4비트는 이진 디코더를 사용 하였으며, ULSB 3비트와 MSB 3비트는 온도계 디코더를 사용한 혼합구조를 채택하였다. 구현된 D/A 변환기의 측정결과, 샘플링 주파수가 80MHz, 입력 주파수 1MHz에서 SFDR은 60.42 dBc, 유효비트수는 8.75 비트를 보여주었다. INL/DNL은 ${\pm}$0.38LSB/${\pm}$0.32LSB로 측정되었으며, 글리치 에너지는 4.6 $pV{\cdot}s$로 나타났다. 전력 소모는 1.8V 전원전압에서 최대 속도인 80MHz일 때 48mW로 측정되었다.

Keywords

References

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