한국통신학회논문지 (The Journal of Korean Institute of Communications and Information Sciences)

  • 제35권5A호
  • /
  • Pages.504-512
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  • 2010
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  • 1226-4717(pISSN)
  • /
  • 2287-3880(eISSN)
한국통신학회 (The Korean Institute of Commucations and Information Sciences)
권호 표지

동기화 기능을 가지는 오차보정회로를 이용한 6비트 800MS/s CMOS A/D 변환기 설계

Design of a 6bit 800MS/s CMOS A/D Converter Using Synchronizable Error Correction Circuit

  • 김원 (LG전자 MC사업부) ;
  • 선종국 (LS 산전) ;
  • 윤광섭 (인하대학교 전자공학과 정보전자 공동 연구소)
  • 투고 : 2010.04.19
  • 발행 : 2010.05.31
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초록

본 논문에서는 무선 USB 칩-셋 내 무선통신시스템단에 적용될 수 있는 6비트 800MS/s 플래쉬 A/D 변환기를 설계하였다. 기존의 A/D 변환기에서 서로 독립적으로 사용되던 오차보정회로단과 동기화단을 하나의 회로로 간소화 시켜서, 하드웨어에 대한 부담을 감소시켰다. 제안한 오차보정회로는 기존의 오차보정회로보다 MOS 트랜지스터의 수를 5개 감소시킬 수 있으며, 오차보정회로 한 개당 면적은 9% 정도 감소하게 된다. 설계된 A/D 변환기는 $0.18{\mu}m$ CMOS 1-poly 6-metal 공정으로 제작되었으며 측정 결과 입력 범위 0.8Vpp, 1.8V의 전원 전압에서 182mW의 전력 소모를 나타내었다. 800MS/s의 변환속도와 128.1MHz의 입력주파수에서 4.0비트의 ENOB을 나타내었다.

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

키워드

참고문헌

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