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Characteristics Analysis Related with Structure and Size of SONOS Flash Memory Device

SONOS 플래시 메모리 소자의 구조와 크기에 따른 특성연구

  • Yang, Seung-Dong (Department of Electronics Engineering, Chungnam National University) ;
  • Oh, Jae-Sub (Nano Patterning Process Team, National Nanofab Center) ;
  • Park, Jeong-Gyu (Department of Electronics Engineering, Chungnam National University) ;
  • Jeong, Kwang-Seok (Department of Electronics Engineering, Chungnam National University) ;
  • Kim, Yu-Mi (Department of Electronics Engineering, Chungnam National University) ;
  • Yun, Ho-Jin (Department of Electronics Engineering, Chungnam National University) ;
  • Choi, Deuk-Sung (Division of Electronics and Information Engineering, Yeungnam College of Science and Technology) ;
  • Lee, Hee-Deok (Department of Electronics Engineering, Chungnam National University) ;
  • Lee, Ga-Won (Department of Electronics Engineering, Chungnam National University)
  • 양승동 (충남대학교 전자전파정보통신공학과) ;
  • 오재섭 (나노종합팹센터 나노패턴팀) ;
  • 박정규 (충남대학교 전자전파정보통신공학과) ;
  • 정광석 (충남대학교 전자전파정보통신공학과) ;
  • 김유미 (충남대학교 전자전파정보통신공학과) ;
  • 윤호진 (충남대학교 전자전파정보통신공학과) ;
  • 최득성 (영남이공대학 전자정보계열) ;
  • 이희덕 (충남대학교 전자전파정보통신공학과) ;
  • 이가원 (충남대학교 전자전파정보통신공학과)
  • Received : 2010.07.22
  • Accepted : 2010.08.19
  • Published : 2010.09.01

Abstract

In this paper, Fin-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory are fabricated and the electrical characteristics are analyzed. Compared to the planar-type SONOS devices, Fin-type SONOS devices show good short channel effect (SCE) immunity due to the enhanced gate controllability. In memory characteristics such as program/erase speed, endurance and data retention, Fin-type SONOS flash memory are also superior to those of conventional planar-type. In addition, Fin-type SONOS device shows improved SCE immunity in accordance with the decrease of Fin width. This is known to be due to the fully depleted mode operation as the Fin width decreases. In Fin-type, however, the memory characteristic improvement is not shown in narrower Fin width. This is thought to be caused by the Fin structure where the electric field of Fin top can interference with the Fin side electric field and be lowered.

Keywords

References

  1. L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T. J. King, Proc. IEEE, 91, 1860 (2003).
  2. International Technology Roadmap for Semiconductors (ITRS) 2001 Edition, Table 38a, 38b (2001).
  3. C. W. Kim, M. K. Kim, and J. W. Lee, Physics and High Technology 13, 2 (2004).
  4. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, Appl. Phys. Lett. 68, 1377 (1996). https://doi.org/10.1063/1.116085
  5. T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hynn, Y. G. Shin, J. N. Han, I. S. Park, U. J. Chung, J. T. Moon, E. Yoon, and J. H. Lee, Symp. VLSI Technol. Dig. Tech. Papers (IEEE, 2003) p. 135
  6. F. Dauge, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah, and B. -Y. Nguyen, Solid-State Electron. 48, 535 (2004). https://doi.org/10.1016/j.sse.2003.09.033
  7. M. Mehrotra and B. J. Baliga, IEDM '93 Tech. Dig. (IEEE, Washington DC, USA, 1993) p. 675.