Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Efficient VLSI Architecture for Factorization in Soft-Decision Reed-Solomon List Decoding

연판정 Reed-Solomon 리스트 디코딩의 Factorization을 위한 효율적인 VLSI 구조

  • Lee, Sung-Man (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea) ;
  • Park, Tae-Guen (Department of Information, Communication, and Electronic Engineering, The Catholic University of Korea)
  • 이성만 (가톨릭대학교 정보통신전자공학부) ;
  • 박태근 (가톨릭대학교 정보통신전자공학부)
  • Received : 2010.05.17
  • Accepted : 2010.11.01
  • Published : 2010.11.25
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Abstract

Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.

Reed-Solomon(RS) 코드는 강력한 에러 정정 능력으로 널리 사용된다. 최근 Sudan에 의해 Reed-Solomon 코드의 리스트 디코딩 알고리즘이 정립되었다. 리스트 디코더는 일반적인 디코더보다 더 큰 디코딩 반경을 가지며 하나 이상의 코드를 찾아낸다. 리스트 디코더는 복잡도와 latency가 매우 큰 Interpolation 과 Factorization 단계를 포함하므로 효율적인 하드웨어 설계가 필요하다. Factorization 은 latency가 매 단계마다 변하는 특성을 가져 복잡도가 높으며, 하드웨어 효율 저하의 문제가 발생한다. 본 논문에서는 하드웨어의 재사용을 높인 구조와 알고리즘의 효율적인 처리 스케쥴을 제안한다. 제안한 구조는 각 단계를 작은 단위의 R-MAC 유닛으로 나누어 매 단계마다 하드웨어를 재구성하여 처리함으로서 높은 하드웨어 효율과 효율적인 메모리 구조를 통해 복잡도가 낮은 순차처리를 적용하면서도 높은 처리량을 보이며, 여러 가지 어플리케이션에 적용가능하다. 제안한 구조는 동부 아남 $0.18{\mu}m$ 표준 셀 라이브러리를 사용하여 합성한 결과 최대 동작 주파수는 330MHz이다.

Keywords

References

  1. R. E. Blahut, Theory and practice of Error Control Codes, Addison-Wesley, Reading MA, 1983.
  2. M. Sudan, "Decoding of Reed-solomon codes beyond the error correction bound," J. complexity, vol. 12, pp. 180-193, 1997.
  3. V. Guruswami and M. Sudan, "Improved decoding of Reed-Solomon and algebraic- geometric codes," IEEE Trans. Inf. Theory, vol. 45, no. 6, pp. 1755-1764, Sep. 1999.
  4. R. Koetter and A. Vardy, "Algebraic soft-ecision decoding of Reed-Solomon codes," IEEE Trans. Inf. Theory, vol. 49, no. 11, pp. 2809-2825, Nov. 2003. https://doi.org/10.1109/TIT.2003.819332
  5. W. J. Gross, F. R. Kschischang, R. Koetter, and P. Gulak, "Simulation results for algebraic soft-decision decoding of Reed-Solomon codes," in Proc. 21st Biennial symp. Commun., pp. 356-360, 2002.
  6. W. J. Gross, F. R. Kschischang, R. Koetter, and P. Gulak, "Applications of algebraic soft-decision decoding of Reed-Solomon codes," IEEE Trans. Commun., vol. 54, no. 7, pp. 1224-1234, Jul. 2006. https://doi.org/10.1109/TCOMM.2006.877972
  7. I. S. Reed and G. Solomon, "Polynomial codes over certain finite fields," SIAM Journal of Applied Mathematics, vol. 8, pp. 300-304, 1960. https://doi.org/10.1137/0108018
  8. R. M. Roth and G. Ruckenstein, "Efficient decoding of Reed-Solomon codes beyond half the minimum distance," IEEE Trans. Inform. Theory, vol. 46, pp.246-258, 2000. https://doi.org/10.1109/18.817522
  9. X. Zhang and K. Parhi, "Fast factorization architecture in soft decision Reed-Solomon decoding," IEEE Trans. VLSI. Syst., vol. 13, no. 4, pp. 413-426, April. 2005. https://doi.org/10.1109/TVLSI.2004.842914
  10. X. Zhang, "Further exploring the strength of prediction in the factorization of soft-decision Reed-Solomon decoding," IEEE Trans. VLSI. Syst., vol. 15, no. 7, pp. 811-820, July. 2007. https://doi.org/10.1109/TVLSI.2007.899238
  11. J. Ma, A. Vardy, and Z. Wang, "Low-latency factorization arhitecture for algebraic soft- decision decoding of Reed-Solomon codes," IEEE Trans. VLSI. Syst., vol. 15, no. 11, pp. 1225-1238, Nov. 2007. https://doi.org/10.1109/TVLSI.2007.904173
  12. A. Ahmed, R. Koetter, and N. Shanbhag, "VLSI architectures for soft-decision decoding of Reed-Solomon codes," in Proc. ICC, 2004, pp. 2584-2590.
  13. R. Koetter and A. Vardy, "A Complexity Reducing Transformation in Algebraic List Decoding of Reed-Solomon Codes," IEEE ITW2003, pp. 10-13, Paris, France, Mar. 2003.
  14. Z. Wang and J. Ma, "High-speed interpolation architecture for soft-decision decoding of Reed-Solomon codes," IEEE Trans. VLSI systems, vol. 14, no. 9, pp. 937-950, Sep. 2006. https://doi.org/10.1109/TVLSI.2006.884046
  15. W. J. Gross, F. R. Kschischang, and P. Gulak, "Architecture and implementation of an interpolation processor for soft-decision Reed- solomon decoding," IEEE Trans. VLSI systems, vol. 15, no. 3, pp. 309-318, Mar. 2007. https://doi.org/10.1109/TVLSI.2007.893609