Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A Gate Delay Model Considering Temporal Proximity of Multiple Input Switching

다중 입력 변화의 시간적 근접성을 고려한 게이트 지연 시간 모델

  • Shin, Jang-Hyuk (Department of Computer Science & engineering, Sogang University) ;
  • Kim, Ju-Ho (Department of Computer Science & engineering, Sogang University)
  • 신장혁 (서강대학교 컴퓨터공학과) ;
  • 김주호 (서강대학교 컴퓨터공학과)
  • Published : 2010.02.25
Download PDF
⟨ Previous Next ⟩

Abstract

Conventional cell characterization does not consider Multiple Input Switching(MIS). Since the impact of MIS on gate delay variation is large, it is not possible to predict the accurate gate delay with the conventional cell characterization. We observed the maximum 46% difference in gate delay due tn MIS. In this paper, we propose a gate delay model considering the delay variation caused by the temporal proximity of MIS. The proposed model calculates the delay variation using the Radial Basis Function. The experimental results show that the proposed method can more accurately predict the gate delay when MIS occurs.

기존의 셀 특성 분석은 다중 입력 변화를 고려하지 않고 셀 특성 분석을 수행한다. 다중 입력 변화가 시간적 근접성에 따라 게이트 지연 시간에 미치는 영향이 커지면서, 기존의 셀 특성 분석으로는 정확한 게이트 지연 시간을 예측하기가 어려워지게 되었다. 다중 입력 변화의 영향으로 인하여 게이트 지연 시간이 최대 46%까지 차이가 나는 것을 실험을 통하여 확인하였다. 본 논문에서는 다중 입력 변화의 시간적 근접성으로 인한 지연 시간 변화를 고려한 게이트 지연 시간 모델을 제안하였다. 제안된 모델은 Radial Basis Function (RBF)을 이용하여 지연 시간 변화량을 계산한다. 제안된 방법이 다중 입력 변화가 발생하였을 때, 보다 정확하게 게이트 지연 시간을 예측하는 것을 실험결과를 통하여 확인하였다.

Keywords

References

  1. T. Fukuoka, A. Tsuchiya, H. Onodera, 'Statistical gate delay model for Multiple Input Switching,' Design Automation Conference, 2008. ASPDAC 2008. Asia and South Pacific, 21-24 March 2008 Page(s):286-291 https://doi.org/10.1109/ASPDAC.2008.4483959
  2. V. Chandramouli, K.A. Sakallah, 'Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time, ' Design Automation Conference Proceedings 1996, 33rd, 3-7 June 1996 Page(s):617-622
  3. J. Sridharan, T. Chen, 'Gate delay modeling with multiple input switching for static (statistical) timing analysis,' VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on, Digital Object Identifier 10.1109/VLSID.2006.92
  4. N. Abdallah, P. Bazargan-Sabet, 'Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven Simulation,' System Theory, 2006 Proceeding of the Thirty-Eighth Southeastern Symposium on, 5-7 March 2006 Page(s):185-189 https://doi.org/10.1109/SSST.2006.1619069
  5. A. Agarwal, F. Dartu, D. Blaauw, 'Statistical gate delay model considering multiple input switching,' Design Automation Conference, 2004. Proceedings. 41st, 2004 Page(s):658 -663
  6. S. Yanamanamanda, Jun Li, J. Wang, 'Uncertainty modeling of gate delay considering multiple input switching,' Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, 23-26 May 2005 Page(s):2457-2460 Vol. 3 https://doi.org/10.1109/ISCAS.2005.1465123
  7. Liang-Chi Chen, S.K. Gupta, M.A. Breuer, 'A new gate delay model for simultaneous switching and its applications,' Design Automation Conference 2001, Page(s):289 -294, 2001
  8. O. Schall, M. Samozino, 'Surface from Scattered Points,' a Brief Survey of Recent Developments. 1st International Workshop on Semantic Virtual Environments, Page(s): 138-147, 2005