산업공학 (IE interfaces)

  • 제23권3호
  • /
  • Pages.229-238
  • /
  • 2010
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  • 1225-0996(pISSN)
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  • 2234-6465(eISSN)
대한산업공학회 (Korean Institute of Industrial Engineers)
권호 표지

유전알고리즘과 커널 부분최소제곱회귀를 이용한 반도체 공정의 가상계측 모델 개발

Development of Virtual Metrology Models in Semiconductor Manufacturing Using Genetic Algorithm and Kernel Partial Least Squares Regression

  • 김보건 (삼성전자 메모리 사업부) ;
  • 염봉진 (KAIST 산업 및 시스템 공학과)
  • Kim, Bo-Keon (Memory Division, Samsung Electronics) ;
  • Yum, Bong-Jin (Department of Industrial and System Engineering, KAIST)
  • 투고 : 2009.12.23
  • 심사 : 2010.04.06
  • 발행 : 2010.09.01
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초록

Virtual metrology (VM), a critical component of semiconductor manufacturing, is an efficient way of assessing the quality of wafers not actually measured. This is done based on a model between equipment sensor data (obtained for all wafers) and the quality characteristics of wafers actually measured. This paper considers principal component regression (PCR), partial least squares regression (PLSR), kernel PCR (KPCR), and kernel PLSR (KPLSR) as VM models. For each regression model, two cases are considered. One utilizes all explanatory variables in developing a model, and the other selects significant variables using the genetic algorithm (GA). The prediction performances of 8 regression models are compared for the short- and long-term etch process data. It is found among others that the GA-KPLSR model performs best for both types of data. Especially, its prediction ability is within the requirement for the short-term data implying that it can be used to implement VM for real etch processes.

키워드

참고문헌

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