JSTS:Journal of Semiconductor Technology and Science

  • 제10권4호
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  • Pages.292-299
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  • 2010
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Timing Analysis Techniques Review for sub-30 nm Circuit Designs

  • 투고 : 2010.12.01
  • 발행 : 2010.12.31
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초록

With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

키워드

참고문헌

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피인용 문헌

  1. Debug Port Protection Mechanism for Secure Embedded Devices vol.12, pp.2, 2012, https://doi.org/10.5573/JSTS.2012.12.2.240