참고문헌
- W. Lu, P. Xie, and C. M. Lieber, “Nanowire Transistor Performance Limits and Applications,” IEEE Trans. Electron Dev., vol. 55, no. 11, pp. 2859-2876, Nov. 2008. https://doi.org/10.1109/TED.2008.2005158
- C. M. Lieber and Z. L. Wang, “Functional nanowires,” MRS Bull. vol. 32, no. 2, pp. 99-108, 2007. https://doi.org/10.1557/mrs2007.41
- R. S. Friedman, M. C. McAlpine, D. S. Ricketts, D. Ham, and C. M. Lieber, “High-speed integrated nanowire circuits,” Nature, vol. 434, pp. 1085, 2005. https://doi.org/10.1038/4341085a
- Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K. H. Kim, and C. M. Lieber, “Logic gates and ... from assembled nanowire building blocks,” Science, vol. 294, pp. 1313-1317, 2001. https://doi.org/10.1126/science.1066192
- Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath, and C. M. Lieber, “Nanowire crossbar arrays as address decoders for integrated nanosystems,” Science, vol. 302, pp. 1377-1379, 2003. https://doi.org/10.1126/science.1090899
- J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, “Ge/Si nanowire heterostructures as high-performance field-effect transistors,” Nature, vol. 441, pp. 489-493, 2006. https://doi.org/10.1038/nature04796
- Y. W. Heo, L. C. Tien, Y. Kwon, D. P. Norton, S. J. Pearton, B. S. Kang, and F. Ren, “Depletion-mode ZnO nanowire field-effect transistor,” Appl. Phys. Lett. vol. 85, pp. 2274-2276, 2004. https://doi.org/10.1063/1.1794351
- S. A. Dayeh, D. P. R. Aplin, X. Zhou, P. K. L. Yu, E. T. Yu, and D. Wang, “High electron mobility InAs nanowire field-effect transistors,” Small, vol. 3, pp. 326-332, 2007. https://doi.org/10.1002/smll.200600379
- H.-Y. Cha, H. Wu, M. Chandrashekhar, Y. C. Choi, S. Chae, G. Koley, and M. G. Spencer, “Fabrication and characterization of pre-aligned gallium nitride nanowire field-effect transistors,” Nanotechnol., vol. 17, pp. 1264-1271, 2006. https://doi.org/10.1088/0957-4484/17/5/018
-
D. Wang, Q. Wang, A. Javey, R. Tu, H. Dai, H. Kim, P. C. Mclntyre, T. Krishnamohan, and K. C. Saraswat, “Germanium nanowire field-effect transistors with SiO2 and high-
${\kappa}$ HfO2 gate dielectrics,” Appl. Phys. Lett., vol. 83, pp. 2432-2434, 2003. https://doi.org/10.1063/1.1611644 - W. I. Park, J. S. Kim, G.-C. Yi, M. H. Bae, and H.-J. Lee, “Fabrication and electrical characteristics of high performance ZnO nanorod field effect transistors,” Appl. Phys. Lett., vol. 85, pp. 5052-5054, 2004. https://doi.org/10.1063/1.1821648
- S. M. Koo, M. D. Edelstein, Q. Li, C. A. Richter, and E. M. Vogel, “Silicon nanowires as enhancement-mode Schottky barrier field-effect transistors”, Nanotechnol., vol. 16, pp. 1482-1485, 2006
- O. Hayden, M. T. Bjork, H. Schmid H, H. Riel, U. Drechsler, S. F. Karg, E. Lortscher, and W. Riess, “Fully-Depleted Nanowire Field Effect Transistor in Inversion Mode,” Small, vol. 3, pp. 230-234, 2007. https://doi.org/10.1002/smll.200600325
- T. L. Wade, X. Hoffer, A. D. Mohammed, J.-F. Dayen, D. Pribat, and J.-E. Wegrowe, “Nanoporous alumina wire templates for surrounding-gate nanowire transistors,” Nanotechnol., vol. 18, pp. 125201-125204, 2007. https://doi.org/10.1088/0957-4484/18/12/125201
- Z. Y. Zhang, C. H. Jin, X. L. Liang, Q. Chen, and L. M. Peng, “Current-voltage characteristics and parameter retrieval of semiconducting nanowires,” Appl. Phys. Lett., vol. 88, pp. 073102, 2006. https://doi.org/10.1063/1.2177362
- S. H. Lee, Y. S. Yu, S. W. Hwang, and D. Ahn, “SPICE-compatible New Silicon Nanowire Field-Effect Transistors (SNWFETS) Model,” IEEE Trans. Nanotechnol., vol. 8, no. 5, pp. 643-649, 2009. https://doi.org/10.1109/TNANO.2009.2019724
- Y. S. Yu, S. H. Lee, J. H. Oh, H. J. Kim, S. W. Hwang, and D. Ahn, “A compact analytical current conduction model for depletion-mode n-type nanowire field-effect transistor (NWFET) with bottom-gate structure,” Semicond. Sci. Technol., vol. 23, pp. 035025, 2008. https://doi.org/10.1088/0268-1242/23/3/035025
- C. Y. Yim, D. Y. Jeon, K. H. Kim, G. T. Ki, Y. S. Woo, S. Roth, J. S. Lee, and S. Kim, “Electrical Properties of the ZnO Nanowire Transistor and its Analysis with Equivalent Circuit Model,” J. Kor. Phys. Soc., vol. 48, pp. 1565-1569, 2006.
- J.-P. Colinge, “Conduction Mechanism in Thin-Film Accumulation-Mode SOI p-Channel MOSFET's,” IEEE Trans. Electron Dev., vol. 37, pp. 718-723, 1990. https://doi.org/10.1109/16.47777
- S. H. Lee, Y. S. Yu, S. W. Hwang, and D. Ahn, “Equivalent Circuit Model of Semiconductor Nanowire Diode by SPICE”, J. Nanoscience Nanotechnol., vol. 7, no. 11, pp. 4089-4093, 2007. https://doi.org/10.1166/jnn.2007.012
- Agilent Technologies 2003 Advanced Design System.
피인용 문헌
- Analyses on Small-Signal Parameters and Radio-Frequency Modeling of Gate-All-Around Tunneling Field-Effect Transistors vol.58, pp.12, 2011, https://doi.org/10.1109/TED.2011.2167335