JSTS:Journal of Semiconductor Technology and Science

  • 제10권1호
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  • Pages.66-77
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  • 2010
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

  • Gupta, Ritesh (Semiconductor Device Research Laboratory Department of Electronic Science, University of Delhi South Campus) ;
  • Kaur, Ravneet (Acharya Narendra Dev College, University of Delhi Department of Electronics) ;
  • Aggarwal, Sandeep Kr (HRMITM, GGSIP University) ;
  • Gupta, Mridula (Semiconductor Device Research Laboratory Department of Electronic Science, University of Delhi South Campus) ;
  • Gupta, R.S. (Semiconductor Device Research Laboratory Department of Electronic Science, University of Delhi South Campus)
  • 투고 : 2009.11.15
  • 발행 : 2010.03.31
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초록

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

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