참고문헌
- International technology roadmap for semiconductor 2006 edition. Available from: (http://public.itrs.net)
- F. Balestra, S. Cristoloveanu, M. Benachir, J. Birni and T. Elewa, "Double gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance", IEEE Electron Device Letters, vol. 8, no. 10, pp. 410–412, 1987 https://doi.org/10.1109/EDL.1987.26677
- R. H. Yan, A. Ourmazd and K. F. Lee, "Scaling the Si MOSFET: from bulk to SOI to bulk", IEEE Trans Electron Devices, vol. 39, no. 7, pp. 1704–1710, 1992 https://doi.org/10.1109/16.141237
- M. Ieong, E. Jones, T. Kanarsky, Z. Ren, O. Dokumaci, R. Roy, L. Shi, T. Furukawa, Y. Taur, R. Miller, and H.-S.P. Wong, "Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs," IEDM Tech. Dig., pp. 441-444, 2001
- J.M. Hergenrother, D. Monroe, F.P. Klemens, A. Komblit, G.R. Weber, W.M. Mansfield, R. Baker, F.H. Baumann, K.J. Bolan, J.E. Bower, N.A. Ciampa, R.A. Cirelli, J.I. Colonell, D.J. Eaglesham, J. Frac-koviak, H.J. Gossmann, M.L. Green, S.J. Hillenius, C.A. King, R.N. Kleiman, W.Y.C. Lai, J.T. Lee, C.R.C. Liu, H.L. Maynard, M.D. Morris, S. Oh, H.C. Pai, S.C.S. Rafferty, J.M. Rosamilia, T.W. Sorsch, and H.H. Vuong, "The Vertical Replace-ment Gate (VRG) MOSFET: A 50-nm vertical MOSFET with lithography independent gate length," IEDM Tech. Dig., pp. 75-78, 1999
- B. Yu, H. Wang, A. Joshi, Q Xiang, E. Ibok, and M-R. Lin, "15nm gate length planar CMOS transistor," IEDM Tech. Dig., pp. 937-940, 2001
- J. Kedzierski, P. Xuan, E.H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide source/drain thin body MOSFETs for the 20 nm gate length regime," IEDM Tech. Dig., pp. 57-60, 2000
- D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A fully depleted lean-channel transistor (DELTA)—A novel vertical ultra thin SOI MOSFET," IEDM Tech. Dig., pp. 833-836, 1989
- J. Kedzierski, D.M. Fried, E.J. Nowak, T. Kanarsky, J.H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R.A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C.P. Willets, A. Johnson, S.P. Cole, H.E. Young, N. Carpenter, D. Rakowski, B.A. Rainey, P.E. Cottrell, M. Ieong, and H.-S.P. Wong, "High-performance symmetric-gate and CMOS-compatible Vt asymmetric- gate FinFET devices," IEDM Tech. Dig., pp. 437-440, 2001
- J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarski, Y. Zhang, R. Roy, D. Boyd, D. Fried and H.S.P. Wong, "Extension and source/drain design for high performance FinFET devices", IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, 2003 https://doi.org/10.1109/TED.2003.811412
- A. Dixit, A. Kottantharayil, N. Collaert, M. Good-win, M. Jurczak and K De Meyer, "Analysis of the parasitic S/D resistance in multiple-gate FETs", IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 1132-1140, 2005 https://doi.org/10.1109/TED.2005.848098
- X. Wu, P. C. H. Chan and M. Chan, "Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET", IEEE Tran. Elec. Dev., vol. 52, no. 1, pp. 63-68, Jan. 2005 https://doi.org/10.1109/TED.2004.841334
- J.G. Fossum, M.M. Chowdhury, V.P. Trivedi, T.-J. King, Y.-K. Choi, J. An and B. Yu, "Physical insights on design and modeling of nanoscale FinFETs", IEDM Tech. Dig., pp. 679-682, 2003
- F. Boeuf, T. Skotnicki, S. Monfray, C. Julien, D. Dutartre, J. Martins, P. Mazoyer, R. Palla, B. Tavel, P. Ribot, E. Sondergard and A. Sanquer, "16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimization", IEDM Tech. Dig., pp. 637-640, 2001
- B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin and D. Kyser, "FinFET scaling to 10 nm gate length", IEDM Tech. Dig., pp. 251-254, 2002
-
E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, T.C. Lim, O. Rozeau, F. Danneville, P. Coronel, T. Skotnicki, S. Deleonibus and O. Faynot, "First internal spacers' introduction in record high Ion/Ioff
$TiN/HfO_2 $ gate multichannel MOSFET satisfying both high-performance and low standby power requirements", IEEE Electron Device Letters, vol. 30, no. 2, pp. 148-151, 2009 https://doi.org/10.1109/LED.2008.2009008 - N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda and J. Ida, "Undoped thin film FD-SOI CMOS with source/ drain-to-gate non-overlapped structure for ultra low leak applications", IEEE SOI Conference, pp. 176-177, 2005
- R. J. Luyken, T. Schultz, J. Hartwich, L. Dreeskornfeld, M. Stadele and L. Risch, "Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime", Solid–State Electronics, vol. 47, no, 7, pp. 1199–1203, 2003 https://doi.org/10.1016/S0038-1101(03)00038-8
- A. Kawamoto, S. Sato and Y. Omura, "Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs", IEEE Trans Electron Devices, vol. 51, no. 6, pp. 907–913, 2004 https://doi.org/10.1109/TED.2004.827360
- R. S. Shenoy and K. C. Saraswat, "Optimisation of extrinsic source/drain resistance in ultrathin body double-gate FETs", IEEE Trans Nanotechnology, vol. 2, no. 4, pp. 265–270, 2003 https://doi.org/10.1109/TNANO.2003.820780
- T. C. Lim and G. A. Armstrong, "Parameter sensitivity for optimal design of 65 nm node double gate SOI transistors", Solid–State Electronics, vol. 49, no. 6, pp. 1034–1043, 2005 https://doi.org/10.1016/j.sse.2005.03.023
- A. Kranti and G. A. Armstrong, "Performance assessment of nanoscale double and triple gate FinFETs", Semiconductor Science and Technology, vol. 21, no. 4, pp. 409–421, 2006 https://doi.org/10.1088/0268-1242/21/4/002
- Rashmi, A. Kranti and G.A. Armstrong, "6-T SRAM cell design with nanoscale double gate SOI MOSFETs: impact of source/drain engineering and circuit topology", Semiconductor Science and Technology, vol. 23, no. 7, article 075049, 2008 https://doi.org/10.1088/0268-1242/23/7/075049
- A. Kranti and G. A. Armstrong, "Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations", Solid–State Electronics, vol. 50, no. 3, pp. 437–447, 2006 https://doi.org/10.1016/j.sse.2006.02.012
- A. Kranti, Y. Hao and G.A. Armstrong, "Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications", Semiconductor Science and Technology, vol. 23, no. 4, article 045001, 2008 https://doi.org/10.1088/0268-1242/23/4/045001
- C.-W. Lee, D. Lederer, A. Afzalian, R. Yan, N. Dehdashti, W. Xiong and J.-P. Colinge, "Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs", Solid-State Electronics, vol. 52, no. 11, pp. 1815-1820, 2008 https://doi.org/10.1016/j.sse.2008.09.006
- A.B. Sachid, C.R. Manoj, D.K. Sharma, and V.R. Rao, "Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization", IEEE Electron Device Letters, vol. 29, no. 1, pp. 128-130, 2008 https://doi.org/10.1109/LED.2007.911974
- [C.R. Manoj and V.R. Rao, "Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs", IEEE Electron Device Letters, vol. 28, no. 4, pp. 295-287, 2007 https://doi.org/10.1109/LED.2007.892365
- S. Sharma and P. Kumar, "Optimizing effective channel length to minimize short channel effects in sub-50 nm single/double gate SOI MOSFETs", Journal of Semiconductor Technology and Science, vol. 8, no. 2, pp. 170-177, 2008 https://doi.org/10.5573/JSTS.2008.8.2.170
- T.C. Lim and G.A. Armstrong, "Scaling issues for analogue circuits using double gate SOI transistors", Solid–State Electronics, vol. 51, no. 2, pp. 320-327, 2007 https://doi.org/10.1016/j.sse.2007.01.006
- A. Kranti and G.A. Armstrong, "High tolerance to gate misalignment in low voltage gate–underlap double gate MOSFETs", IEEE Electron Device Letters, vol. 29, no. 5, pp. 503-505, 2008 https://doi.org/10.1109/LED.2008.920281
- A. Kranti and G.A. Armstrong, "Design and optimization of FinFETs for ultra–low–voltage analog applications", IEEE Trans. Electron Devices, vol. 54, no.12, pp. 3308-3316, 2007 https://doi.org/10.1109/TED.2007.908596
- A. Kranti and G.A. Armstrong, "Source/Drain extension region engineering in FinFETs for low-voltage analog applications", IEEE Electron Device Letters, vol. 28, no. 2, pp. 139–141, 2007 https://doi.org/10.1109/LED.2006.889239
- H. Shang, K.-L. Lee, P. Kozlowski, C. D'Emic, I. Babich, E. Siroski, M. Ieong, H.-S.P. Wong, and K. Guarini, "Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate," IEEE Electron Device Letters, vol. 25, no. 3, pp. 135–137, 2004 https://doi.org/10.1109/LED.2003.823060
- K. C. Saranswat, C. O. Chui, T. Krishnamohan, A. Nayfeh, and P. McIntyre, "Ge based high perfor-mance nanoscale MOSFETs," Microelectronic Engineering, vol. 80, no. 1, pp. 15–21, Jun. 2005 https://doi.org/10.1016/j.mee.2005.04.038
- H. Shang, M. M. Frank, E. P. Gusev, J. O. Chu, S. W. Bedell, K. W. Guarini, and M. Ieong, "Germanium channel MOSFETs: opportunities and challenges," IBM J. Res. Develop., vol. 50, no. 4-5, pp. 377–386, 2006 https://doi.org/10.1147/rd.504.0377
-
R. S. Johnson, H. Niimi, and G. Lucovsky, "New approach for the fabrication of device-quality
$Ge/GeO_2/SiO_2 $ interfaces using low temperature remoted plasma processing," J. Vac. Sci. Technol., vol. 18, no. 4, pp. 1230–1233, 2000 https://doi.org/10.1116/1.582331 - N. Lu, W. Bai, A. Ramirez, C. Mouli, A. Ritenour, M. L. Lee, D. Antoniadis, and D. L. Kwong, "Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric," Applied Physics Letters, vol. 87, no. 5, pp. 51922–51924, 2005 https://doi.org/10.1063/1.2001757
- D. J. Hymes and J. J. Rosenberg, "Grow and materials characterization of native oxynitride thin films on germanium," Journal of Electrochemical Society, vol. 135, no. 4, pp. 961–965, 1988 https://doi.org/10.1149/1.2095851
- H. Shang, H. Okorn-Schimdt, J. Ott, P. Kozlowski, S. Steen, E. C. Jones, and H.-S. P. Wong, "Electrical characterization of germanium p-channel MOSFETs," IEEE Electron Device Letters, vol. 24, no. 4, pp. 242–244, 2003 https://doi.org/10.1109/LED.2003.810879
- S. K. Mandal, S. Chakraborty, and C. K. Maiti, "Ge-channel p-MOSFETs with ZrO2 gate dielectrics," Microelectronic Engineering, vol. 81, no. 2–4, pp. 206–211, 2005 https://doi.org/10.1016/j.mee.2005.03.008
- W. Bai, ". Lu, A. P. Ritenour, M. L. Lee, D. A. Antoniadis, and D.-L. Kwong, “The electrical properties of HfO2 dielectric on germanium and the substrate doping effect," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2551–2558, 2006 https://doi.org/10.1109/TED.2006.882276
-
C. O. Chui, H. Kim, D. Chi, B. Triplett, P. C. McIntyre, and K. C. Saraswat, "A sub-400
$^{\circ}C$ germanium MOSFET technology with high-k dielectric and metal gate," IEDM Tech. Dig., pp. 437–440, 2002 - H. Shang, H. Okorn-Schmidt, K. K. Chan, M. Copel, J. A. Ott, P. M. Kozlowski, S. E. Steen, S. A. Cordes, H.-S. P. Wong, E. C. Jones, and W. E. Haensch, "High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric," IEDM Tech. Dig., pp. 441–444, 2002
- K. K. Young, "Short channel effects in fully depleted SOI MOSFETs", IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399–401, 1989 https://doi.org/10.1109/16.19942
- K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie and Y. Arimoto, "Scaling theory for double-gate SOI MOSFETs", IEEE Trans Electron Devices, vol. 40, no. 12, pp. 2326–2329, 1993 https://doi.org/10.1109/16.249482
- Y. Tosaka, K. Suzuki and T. Sugii, "Scaling Parameter Dependent Model for Subthreshold Swing (S) in Double-Gate SO1 MOSFET's", IEEE Electron Device Letters, vol. 15, no. 11, pp. 466–468, 1994 https://doi.org/10.1109/55.334669
- X. Liang and Y. Taur, "A 2-D Analytical Solution for SCEs in DG MOSFETs", IEEE Trans Electron Devices, vol. 51, no. 8, pp. 1385–1391, 2004 https://doi.org/10.1109/TED.2004.832707
- J.–S. Park, S.–Y. Lee, H. Shin and R. W. Dutton, "Analytical analysis of short-channel effects in MOSFETs for sub-100 nm technology", Electronics Letters, vol. 38, no. 20, 1222-1223, 2002 https://doi.org/10.1049/el:20020797
- D. J. Frank, Y. Taur and H. S. P. Wong, "Genera-lized scale length for two dimensional effects in MOSFETs", IEEE Electron Device Letters, vol. 19, no. 9, vol. 385–387, 1998
-
K. Suzuki and T. Sugii, "Analytical Models for
$n^+-p^+$ double-gate SO1 MOSFET's", IEEE Trans Electron Devices, vol. 42, no. 11, pp. 1940-1948, 1385–1391, 1995 https://doi.org/10.1109/16.469401 - K. Suzuki, Y. Tosaka and T. Sugii, "Analytical threshold voltage model for short channel n+-p+ double gate SOI MOSFET's", IEEE Trans Electron Devices, vol. 43, no. 5, pp. 732-738, 1996 https://doi.org/10.1109/16.491249
- K. Suzuki, Y. Tosaka and T. Sugii, "Analytical threshold voltage model for short channel double gate SOI MOSFET's", IEEE Trans Electron Devices, vol. 43, no. 7, pp. 1166-1168, 1996 https://doi.org/10.1109/16.502429
- Q. Chen, B. Agrawal and J.D. Meindl, "A compre-hensive analytical subthreshold swing (S) Model for double-gate MOSFETs", IEEE Trans Electron Devices, vol. 49, no. 6, pp. 1086-1090, 2002 https://doi.org/10.1109/TED.2002.1003757
- A. Kranti and G. A. Armstrong, "Optimization of the source/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFETs with high-κ gate dielectrics", Semiconductor Science and Technology, vol. 21, no. 12, pp. 1563-1572., 2006 https://doi.org/10.1088/0268-1242/21/12/011
- Q. Chen, E. M. Harrell, II and J. D. Meindl, "A Physical Short-Channel Threshold Voltage Model for Undoped Symmetric Double-Gate MOSFETs", IEEE Trans Electron Devices, vol. 50, no. 7, pp. 1631-1637, 2003 https://doi.org/10.1109/TED.2003.813906
- D. Munteanu, J. L. Autran and S. Harrison, "Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivity gate dielectrics", Journal of Non-Crystalline Solids, vol. 351, no. 21-23, pp.1911–1918, 2005 https://doi.org/10.1016/j.jnoncrysol.2005.04.037
피인용 문헌
- Analyses on Small-Signal Parameters and Radio-Frequency Modeling of Gate-All-Around Tunneling Field-Effect Transistors vol.58, pp.12, 2011, https://doi.org/10.1109/TED.2011.2167335