참고문헌
- K. C. Smith, "The prospect for multi- valued logic: a technology and applications view," IEEE Trans. Comput., vol. C-30, No. 9, pp.619-634, Sept. 1981 https://doi.org/10.1109/TC.1981.1675860
- S. L. Hurst, "Multiple-valued logic - its future," IEEE Trans. Comput., vol. C-33, No. 12, pp.1161-1179, Dec. 1984
- J. T. Butler, "Multiple-valued logic in VLSI", IEEE Computer Soc. Press, 1991
- B. Benjauthrit and I. S. Reed, "Galois switching functions and their application," IEEE Trans. Comput., vol. C-25, No. 1, pp.78-86, Jan. 1976 https://doi.org/10.1109/TC.1976.5009207
- K. S. Menger, 'A transform logic networks,' IEEE Trans. Comput., vol. C-18, No. 3, pp.241-250, Mar. 1969 https://doi.org/10.1109/T-C.1969.222637
- C. C. Wang, T. K. Truong, H. M. Shao, L. J. Deutsch, J. K. Omura and I. S. Reed, "VLSI architectures for computing multiplications and inverses in GF(2m)," IEEE Trans. Comput., vol. C-34, No. 8, pp.709-717, Aug. 1985 https://doi.org/10.1109/TC.1985.1676616
- H. M. Shao, T. K. Truong, L. J. Deutch, J. H. Yaeh and I. S. Reed, "A VLSI design of a pipelining Reed-Solomon decoder," IEEE Trans. Comput., vol. C-34, No. 5, pp.393-403, May 1985 https://doi.org/10.1109/TC.1985.1676579
- 성현경, 김흥수, "GF(2m)상의 셀 배열 승산기의 구성," 전자공학회논문지, 제26권, 제4호, pp.81-87, 1989년 4월
- Z. Zilic and Z. Vranesic, "Current-mode CMOS Galois field circuits," Proc. 23rd ISMVL, Sacramento, CA, USA, pp.245- 250, May 1993
- S. P. Onneweer and H. G. Kerkhoff, "Current-mode CMOS high-radix circuits," Proc. 16th ISMVL, Blacksburg, Virginia, USA, pp.60-69, May 1986
- J. T. Butler, J. H. Pugsley and C. B. Silio Jr., "High-speed multiplier uses 50 percent less chip area and power," IEEE Computer, vol. 20, No. 8, pp.109-110, Aug. 1987
- T. Yamakawa, T. Miki and F. Ueno, "The design and fabrication of the current mode fuzzy logic semicustom IC in standard CMOS IC technology," Proc. 15th ISMVL, Kingston, Ontario, Canada, pp.76-82, May 1985
- S. Bandyopadhyay and A. Sengupta, "Algorithms for multiplication in Galois field for implementation using systolic arrays," IEE Proc., vol. 135, Pt. E, No. 6, pp.336-339, Nov. 1988
- K. W. Current, "Current-mode CMOS multiple-valued logic circuits," IEEE J. Solid-State Circuits, vol. 29, No. 2, pp.95-107, Feb. 1994 https://doi.org/10.1109/4.272112
- T. Hanyu and M. Kameyama, "A 200MHz pipelined multiplier using 1.5V supply multiple-valued MOS current- mode circuits with dual-rail source- coupled logic," IEEE J. Solid-State Circuits, vol. 30, No. 11, pp.1239-1245, Nov. 1995 https://doi.org/10.1109/4.475711
- K. Navi, A. Kazeminejad and D. Etiemble, "Performance of CMOS current mode full adders," Proc. 24th ISMVL, Boston, MA, USA, pp.27-34, May 1994
- S. Kawahito, M. Kameyama, T. Higuchi and H. Yamada, "A 32×32-bit multiplier using multiple-valued MOS current-mode circuits," IEEE J. Solid-State Circuits, vol. 23, No. 1, pp.124-132, Feb. 1988 https://doi.org/10.1109/4.268
- H. Fukuda, "Signed-digit CMOS (SD- CMOS) Logic Circuits with Dynamic Operation," Proc. 35th ISMVL, Calgary, Canada, pp.76-82, May 2005
- N. Okada and M. Kameyama, "Low-Power Multiple- Valued Reconfigurable VLSI Using Series-Gating Differential- Pair Circuits," Proc. 37th ISMVL, Oslo, Norway, May 2007
- A. Hirosaki, M. Miura, A. Matsumoto, and T. Hanyu, "Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices," Proc. 38th ISMVL, Dallas, Texas, U.S.A, pp.14-19, May 2008