DOI QR코드

DOI QR Code

전하 포획 플래시 소자를 위한 Al2O3/La2O3/SiO2 다층 박막 구조의 메모리 특성

Memory Characteristics of Al2O3/La2O3/SiO2 Multi-Layer Structures for Charge Trap Flash Devices

  • 차승용 (연세대학교 신소재공학과) ;
  • 김효준 (연세대학교 신소재공학과) ;
  • 최두진 (연세대학교 신소재공학과)
  • Cha, Seung-Yong (Department of Materials Science and Engineering, Yonsei University) ;
  • Kim, Hyo-June (Department of Materials Science and Engineering, Yonsei University) ;
  • Choi, Doo-Jin (Department of Materials Science and Engineering, Yonsei University)
  • 발행 : 2009.09.27

초록

The Charge Trap Flash (CTF) memory device is a replacement candidate for the NAND Flash device. In this study, Pt/$Al_2O_3/La_2O_3/SiO_2$/Si multilayer structures with lanthanum oxide charge trap layers were fabricated for nonvolatile memory device applications. Aluminum oxide films were used as blocking oxides for low power consumption in program/erase operations and reduced charge transports through blocking oxide layers. The thicknesses of $SiO_2$ were from 30 $\AA$ to 50 $\AA$. From the C-V measurement, the largest memory window of 1.3V was obtained in the 40 $\AA$ tunnel oxide specimen, and the 50 $\AA$ tunnel oxide specimen showed the smallest memory window. In the cycling test for reliability, the 30 $\AA$ tunnel oxide sample showed an abrupt memory window reduction due to a high electric field of 9$\sim$10MV/cm through the tunnel oxide while the other samples showed less than a 10% loss of memory window for $10^4$ cycles of program/erase operation. The I-V measurement data of the capacitor structures indicated leakage current values in the order of $10^{-4}A/cm^2$ at 1V. These values are small enough to be used in nonvolatile memory devices, and the sample with tunnel oxide formed at $850^{\circ}C$ showed superior memory characteristics compared to the sample with $750^{\circ}C$ tunnel oxide due to higher concentration of trap sites at the interface region originating from the rough interface.

키워드

참고문헌

  1. International Technology Roadmap for Semiconductors, PIDS (2008)
  2. K. Kim and S. Y. Lee, Microelectron. Eng., 84(9), 1976 (2007) https://doi.org/10.1016/j.mee.2007.04.120
  3. G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan and R. S. Shenoy, IBM J. Res. & Dev., 52(4), 449 (2008) https://doi.org/10.1147/rd.524.0449
  4. M. H. White, D. A. Adams and J. Bu, IEEE Circuit. Dev. Magazine, 16(4), 22 (2000) https://doi.org/10.1109/101.857747
  5. J. A. Felix, J. R. Schwank, D. M. Fleetwood, M. R. Shaneyfelt and E. P. Gusev, Microelectron. Reliab., 44(4), 563 (2004) https://doi.org/10.1016/j.microrel.2003.12.005
  6. T. M. Pan and T. Y. Yu, Appl. Phys. Lett., 92, 112906 (2008) https://doi.org/10.1063/1.2898215
  7. Y. N. Tan, W. K. Chim, B. J. Cho and W. K. Choi, IEEE T. Electron. Dev., 51(7), 1143 (2004) https://doi.org/10.1109/TED.2004.829861
  8. B. Sen, H. Wong, J. Molina, H. Iwai, J. A. Ng, K. Kakushima and C. K. Sarkar, Solid State Electron., 51(3), 475 (2007) https://doi.org/10.1016/j.sse.2007.01.032
  9. S. Jeon, J. H. Han, J. H. Lee, S. Choi, H. Hwang and C. Kim, IEEE T. Electron. Dev., 52(12), 2654 (2005) https://doi.org/10.1109/TED.2005.859691
  10. J. Hwang, Kor. J. Mater. Res., 18(10), 552 (2008) https://doi.org/10.3740/MRSK.2008.18.10.552
  11. H.-M. An, Y. J. Seo, H. D. Kim, K. C. Kim, J.-G. Kim, W.-J. Cho, J.-H. Koh, Y. M. Sung and T. G. Kim, Thin Solid Films, 517(18), 5589 (2009) https://doi.org/10.1016/j.tsf.2009.03.184
  12. C. M. Osburn and D. W. Ormond, J. Electrochem. Soc., 119, 591 (1972) https://doi.org/10.1149/1.2404268
  13. Y. Shi, K. Saito, H. Ishikuro and T. Hiramoto, J. Appl. Phys., 84(4), 2358 (1998) https://doi.org/10.1063/1.368346