References
- R.Ho, K.W.Mai, and M.A, "The Future of Wires", Proc. IEEE, vol. 89, April 2001 https://doi.org/10.1109/5.920580
- AMBA AHB Interconnection Matrix, www.synopsys.com/products/designware/amba_solutions.html
- S.Pasricha, N.Dutt, and M. Ben-Romdhane, "Constraint-Driven Bus Matrix Synthesis for MPSoC", ASPDAC 2006 https://doi.org/10.1109/ASPDAC.2006.1594641
- AMBA AXI Protocol v1.0 Specification. http://www.arm.com/products/solutions/AMBA3AXI.html
- ARM SoC Designer http://www.arm.com/products/DevTools/SoCDesigner.html
- M. Gasteier and M. Glesner, "Bus-based communication synthesis on system level," ACM TODAES 1999 https://doi.org/10.1145/298865.298866
- S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Fast Exploration of Bus-based On-chip Communication Architectures," CODES+ISSS 2004 https://doi.org/10.1145/1016720.1016778
- S.Pasricha, N.Dutt, E.Bozorgzadeh, and M.Ben-Romdhane, "Floorplan-aware Automated Synthesis of Bus-based Communication Architectures," In Proc. of DAC 2005
- A. Pinto, L. Carloni, and A. Sangiovanni-Vincentelli, "Constraint driven communication synthesis," DAC 2002 https://doi.org/10.1145/513918.514114
- D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, "Automatic generation of application-specific archi¬tectures for heterogeneous multiprocessor system-on-chip," DAC 2001 https://doi.org/10.1145/378239.379015
- K. Srinivasan, et al, "Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures," ICCD 2004 https://doi.org/10.1109/ICCD.2004.1347957
- D. Bertozzi, et al., "NoC synthesis flow for customized domain specific multiprocessor systems-on-chip," IEEE TPDS 2005 https://doi.org/10.1109/TPDS.2005.22
- U. Ogras and R. Marculescu, "Energy- and Performance-Driven NoC Communication Architecture Synthesis using a Decomposition Approach," DATE 2005 https://doi.org/10.1109/DATE.2005.137
- A. Pinto, L. P. Carloni, and A. L. Sangiovanni-Vincentelli, "Efficient Synthesis of Networks On Chip," ICCD 2003 https://doi.org/10.1109/ICCD.2003.1240887
- A. Jalabert, S. Murali, L. Benini, and G. De Micheli, "xpipesCompiler: A Tool for instantiating appli-cation specific Networks on Chip," DATE 2004 https://doi.org/10.1109/DATE.2004.1268999
- O. Ogawa, et al, "A Practical Approach for Bus Architecture Optimization at Transaction Level," DATE 2003 https://doi.org/10.1109/DATE.2003.10237
- S. Murali and G. De Micheli, "An Application-Specific Design Methodology for STbus Crossbar Generation", DATE 2004 https://doi.org/10.1109/DATE.2005.50
- ARM AMBA Specification and Multi layer AHB Specification, (rev2.0), http://www.arm.com, 2001
- IBM On-chip CoreConnect Bus Architecture, www.chips.ibm.com/products/coreconnect/index.html
- Benini and G.D.Micheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, Jan. 2002 https://doi.org/10.1109/2.976921
- F. Angiolini, et al., "Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness", DATE 2006 https://doi.org/10.1109/DATE.2006.244033
- ARM documents - System-on-Chip, http://www.arm.com/documentation/SoC/index.html
- Synipsys Design Ware IP - AMBA solutions, http://www.synipsys.com/products/designware/amba\_solution.html
- SonicsMX datasheet, http://www.sonicsinc.com/documents/SMX\_Data\_Sheet.pdf
Cited by
- Topology Synthesis for Low Power Cascaded Crossbar Switches vol.29, pp.12, 2010, https://doi.org/10.1109/TCAD.2010.2072730
- Smart Bus Arbiter for QoS control in H.264 decoders vol.11, pp.1, 2011, https://doi.org/10.5573/JSTS.2011.11.1.033