DOI QR코드

DOI QR Code

Through Silicon Via Filling and Fine Pitch Joining Technology for 3D Electronic Package

3D 전자패키징용 관통실리콘비아의 충진 및 미세피치 접합기술

  • 유세훈 (한국생산기술연구원 용접접합기술지원센터) ;
  • 이창우 (한국생산기술연구원 용접접합기술지원센터)
  • Published : 2009.06.30

Abstract

Keywords

References

  1. M. Tomisaka, H. Yonemura, M. Hoshino, and K. Takahashi, in Solid State Devicesand Materials, 40, Tokyo (2001)
  2. K. Takahashi, in The 2nd Annual Meeting on Electronic SI Technologies, 27, Tokyo (2001)
  3. M. Motoyoshi and M. Koyanagi : 3D-LSI Technology for Image Sensor, Pixel 2008 International Workshop, Batavia, IL, Sep 23-26, 2008
  4. J.T. Norman, M. Perez, S.E. Schulz and T. Waechtler : New precursors for CVD copper metallization, Microelectronic Engineering, 85 (2008) 2159-2163 https://doi.org/10.1016/j.mee.2008.05.036
  5. P. Dixit, X. Chen, J. Miao, and R. Preisser : Effect of improved wettability of silicon-based materials with electrolyte for void free copper deposition in high aspect ratio through-vias, Thin Solid Films, 516 (2008) 5194-5200 https://doi.org/10.1016/j.tsf.2007.07.058
  6. S.-W. Seo, G.-S. Kim : The Film Property and Deposition Process of TSV Inside for 3D Interconnection, Journal of the Microelectronics & Packaging Society, 15-3 (2008) 47-52 (in Korean)
  7. T. Jiang and S. Luo : 3D integration-Present and Future, Proceedings of 10th Electronics Packaging Technology Conferences, 2008, 373-378
  8. R. Beica, P. Siblerud, C. Sharbono and M. Bernt:Proceedings of 10th Electronics Packaging Technology Conferences, 2008, 212-218
  9. O. Luhn, C. Van Hoof, W. Ruythooren, J.-P. Celis : Barrier and seed layer coverage in 3D structures with different aspect ratios using sputtering and ALD processes, Microelectronic Engineering, 85 (2008) 1947-1951 https://doi.org/10.1016/j.mee.2008.06.007
  10. P. Dixit, X. Chen, J. Miao, S. Divakaran and R. Preisser, Applied Surface Sicence, 253 (2007), 8637-8646 https://doi.org/10.1016/j.apsusc.2007.04.067
  11. J.-J. Sun, K. Kondo, T. Okamura, S.-J. Oh, M. Tomisaka, H. yonemura, M. Hoshino and K. Takahashi : Journal of the Electrochemical Society, 150-6 (2003) G355-G358 https://doi.org/10.1149/1.1572154
  12. G.-H. Chang and J.-H. Lee : The Effect of Current Types on Through Via Hole Filling for 3D-SiP Application, Journal of the Microelectronics & Packaging Society, 13-4 (2006) 45-50
  13. S.-E. Lee and J.-H. Lee : Copper Via Filling Using Organic Additives and Wave Current Electroplating, Journal of Microelectronics & Packaging Society, 14-3 (2007) 37-42 (in Korean)
  14. C. Song, Z. Wang, Q. Chen, J. Cai, L. Liu : High aspect ratio copper through-silicon-vias for 3D integration, Microelectronic Engineering, 85 (2008) 1952-1956 https://doi.org/10.1016/j.mee.2008.05.017
  15. S.H. Park, T.S. Oh, Y.S. Eum and J.T. Moon : Interconnection Processes Using Cu Vias for MEMS Sensor Packages, Journal of the Microelectronics & Packaging Society, 14-4 (2007) 63-69 (in Korean)
  16. D. M. Chang, C. H. Ryu, K. Y. Lee, B. H. Cho, J. H. Kim, T. S. Oh, W. J. Lee, and Jin Yu : Development and Evaluation of 3-D SiP with Vertically Interconnected ThroughSilicon Vias(TSV), Proceedings of the Electronics Components Technology conference, 2007, 847-852
  17. Y. K. Jee, J. Yu, K. W. Park, and T. S. Oh : Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package, Journal of Electronic Materials, 38-5 (2009) 685-690 https://doi.org/10.1007/s11664-008-0646-6
  18. K. N. Chen, A. Fan, C. S. Tan and R. Reif : Bonding Parameters of Blanket Copper Wafer Bonding, Journal of Electronic Materials, 35-2 (2006) 230-234 https://doi.org/10.1007/BF02692440
  19. X.F. Ang, A.T. Lin, J. Wei, Z. Chen and C.C. Wong : Low Temperature Copper-Copper Thermocompression Bonding, Proceedings of the Electronics Components Technology conference, 2007, 399-404
  20. K.N. Chen, C.S. Tan, A. Fan and R. Reif : Morphology and Bond Strength of Copper Wafer Bonding, Electrochemical Solid-State Letters, 7-1 (2004) G14-G16 https://doi.org/10.1149/1.1626994
  21. C. S. Tan, K.N Chen, A. Fan and R. Reif : The Effect of Forming Gas Anneal on the Oxygen Content in Bonded Copper Layer, Journal of Electronic Materials, 34-12 (2005) 1598-1602 https://doi.org/10.1007/s11664-005-0171-9
  22. P. Morrow, B. Black, M.J. Kobrinsky, S. Muthukumar, D. Nelson, C.-M. Park, C. Webb : Desgin and Fabrication of 3D Microprocessors, Proceedings of Materials Research Society Symposium, 970 (2007) 0970-Y03-02
  23. T. Mitsuhashi, Y. Egawa, O. Kato, Y. Saeki, H. Kikuchi, S. Uchiyama, K. Shibata, J. Yamada, M. Ishino, H. Ikeda, N. Takahashi, Y. Kurita, M. Komuro, S. Matsui, M. Kawano : Development of 3D-packaging Process Technology for Stacked Memory Chips, Proceedings of Materials Research Society Symposium, 970 (2007) 0970-Y03-06