한국정보과학회논문지:시스템및이론 (Journal of KIISE:Computer Systems and Theory)

한국정보과학회 (Korean Institute of Information Scientists and Engineers)
권호 표지

고정블록을 포함한 CBL 기반 평면계획

Floorplanning with Obstacles(Preplaced Block) based on CBL

  • 강상구 (서강대학교 컴퓨터공학과) ;
  • 임종석 (서강대학교 컴퓨터공학과)
  • 발행 : 2009.06.15
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 고정 블록이 포함된 회로를 대상으로 하는 새로운 CBL 기반 평면계획 방법을 제안한다. 기존의 CBL 기반의 고정블록 평면계획의 문제점을 파악하고 이를 개선하였다. 제안한 방법은 자유 블록 만으로 구성된 CBL에 고정블록을 삽입하여 윈래 CBL과 그 위상이 유사하고 패킹이 가능한 새로운 CBL을 만드는 방법으로 이를 시뮬레이티드 어닐링에 적용하여 평면계획을 수행한다. 실험결과는 우리가 제안한 평면계획 방법이 고정블록을 효과적이고 효율적으로 배치할 수 있음을 보여준다.

In this paper we propose a new CBL-based floorplan method that accommodates pre-placed blocks. We identify the problem of the previous CBL-based pre-placed block floorplan method, and suggest the solution method of this problem. In our method, CBLs consisting of only free blocks are perturbed and maintained during the simulated annealing. Pre-placed blocks are inserted during packing in such a way that the topology of the CBL after insertion of a pre-placed block resembles the topology before insertion. Thus, even with the inclusion of pre-placed blocks, the searching effort via simulated annealing yields acceptable results. Experimental results show that our floorplan method places pre-placed blocks effectively and efficiently.

키워드

참고문헌

  1. M. Sarrafzadeh, C. K. Wong, An introduction to VLSI physical design, McGraw-Hill Companies, Inc., 1996.
  2. Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu, "B*-Trees: a new representation for nonslicing floorplans," in Proc. IEEE/ACM DAC, pp. 458-463, 2000.
  3. S. Dong, X. Hong, S. Chen, X. Qi, R. Wang and J. Gu, "VLSI module placement with pre-placed modules and with consideration of congestion using solution space smoothing," IEICE Trans. Fundamentals, Vol.E86-A, No.12, pp. 3136-3147, 2003.
  4. H. Murata, K. Fujiyoshi, and M. Kaneko, "VLSI/PCB placement with obstacles based on sequence pair," IEEE Trans. CAD, Vol.17, No.1, pp. 60-68, 1998. https://doi.org/10.1109/43.673633
  5. F. Y. Young, and D. F. Wong, "Slicing floorplans with pre-placed modules," in Proc. IEEE/ACM ICCAD, pp. 252-258, 1998.
  6. Y. Ma, S. Dong, X. Hong, Y. Cai, C. K. Cheng, and J. Gu, "VLSI floorplanning with boundary constraints based on corner block list," in Proc. IEEE/ACM ASP-DAC, pp. 509-514, 2001.
  7. F. Y. Young, D. F. Wong, and H. H. Yang, "Slicing floorplans with boundary constraints," IEEE Trans. CAD, Vol.18, No.9, pp. 1385-1389, 1999. https://doi.org/10.1109/43.784129
  8. K. Fujiyoshi, and H. Murata, "Arbitrary convex and concave rectilinear block packing using sequence- pair," in Proc. IEEE/ACM ISPD, pp. 103-110, 1999.
  9. Y. Ma, X. Hong, S. Dong, Y. Cai, C. K. Cheng, and J. Gu, "Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list," in Proc. IEEE/ACM DAC, pp. 770-775, 2001.
  10. F. Y. Young, H. H. Yang, and D. F. Wong, "On extending slicing floorplans to handle L/T-shaped modules and abutment constraints," IEEE Trans. CAD, Vol.20, No.6, pp. 800-807, 2001. https://doi.org/10.1109/43.924833
  11. F. Y. Young, D. F. Wong, and H. H. Yang, "Slicing floorplans with range constraint," IEEE Trans. CAD, Vol.19, No.2, pp. 272-278, 2000. https://doi.org/10.1109/43.828556
  12. S. Chen, S. Dong, X. Hong, Y. Ma, and C. K. Cheng, "VLSI block placement with alignment constraints," IEEE Trans. CAS-II, Vol.53, No.8, pp. 622-626, 2006.
  13. H. Xiang, X. Tang, and D. Wong, "Bus-driven floorplanning," IEEE Trans. CAD, Vol.23, No.11, pp. 1522-1530, 2004. https://doi.org/10.1109/TCAD.2004.836728
  14. E. F. Y. Young, C. C. N. Chu, and M. L. Ho, "Placement constraints in floorplan design," IEEE Trans. VLSI Systems, Vol.12, No.7, pp. 735-745, 2004. https://doi.org/10.1109/TVLSI.2004.830915
  15. S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, "Optimization by simulated annealing," Science, Vol.220, No.4598, pp. 671-680, 1983. https://doi.org/10.1126/science.220.4598.671
  16. H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence pair," IEEE Trans. CAD, Vol.15, No.12, pp. 1518-1524, 1996. https://doi.org/10.1109/43.552084
  17. S. Nakatake, K. Fujiyoshi, H. Murata, and Y. Kajitani, "Module placement on BSG-structure and IC layout application," in Proc. IEEE/ACM ICCAD, pp. 484-491, 1996.
  18. X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C. K. Cheng, and J. Gu, "Corner Block List: an effective and efficient topological representation of nonslicing floorplan," in Proc. IEEE/ACM ICCAD, pp. 8-12, 2000.
  19. S. Zhou, X. Hong, T. Cai, C. K. Cheng, and J. Gu, "ECBL: an extended corner block list with solution space including optimum placement," in Proc. IEEE/ACM ISPD, pp. 150-155, 2001.
  20. 강상구, 신정호, 임종석, "Corner Block List를 이용한 개선된 블록 배치 방법", IEEK SOC Design Conference, pp. 263-268, 2003.
  21. P. N. Guo, and C. K. Cheng, "An O-tree representation of non-slicing floorplan and its applications," in Proc. IEEE/ACM DAC, pp. 268-273, 1999.
  22. K. Sakanushi, Y. Kajitani and D. P. Mehta, "The quarter-state-sequence floorplan representation," IEEE Trans. CAS-I, Vol.50, No.3, pp. 376-386, 2003. https://doi.org/10.1109/TCSI.2003.809442
  23. S. Dhamdhere, N. Zhou and T.-C. Wang, "Module Placement with Pre-Placed Modules Using the Corner Block List Representation," IEEE ISCAS, pp. I-349-I-352, 2002.
  24. K. Koziminski, "Benchmarks for layout synthesis-evolution and current status," in Proc. IEEE/ACM DAC, pp. 265-270, 1991.