A $0.18{\mu}m$ CMOS 3.2-Gb/s 4-PAM Serial Link Receiver Using Current Mode Signaling

Current Mode Signaling 방법을 이용한 $0.18{\mu}m$ CMOS 3.2-Gb/s 4-PAM Serial Link Receiver

  • Received : 2009.08.10
  • Published : 2009.10.25

Abstract

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

본 논문은 $0.18{\mu}m$ CMOS 공정을 이용하여 3.2 Gb/s serial link receiver를 설계하였다. High-speed links의 performance를 제한하는 가장 큰 요소는 transmission channel bandwidth, timing uncertainty가 있다. 이러한 문제점을 해결하기 위한 방법으로 multi-level signaling(4-PAM)을 이용하였다. 추가적으로 전송속도를 높이고 BER를 낮추기 위한 방법으로 current-mode amplifier, CML sampling latch를 사용하였다. 4-PAM receiver의 최대 데이터 전송속도는 3.2 Gb/s이다. BER은 $1.0{\times}10^{-12}$ 이하이며 chip size는 $0.5\;{\times}\;0.6\;mm^2$이고 1.8 V supply voltage에서 49mA current를 소모한다.

Keywords

References

  1. A. Maxim, 'A 3.3V 10Gb/s SiGe limiting transimpedance amplifier using a pseudo differential input and a limiting Cherry-Hooper stage' Radio Frequency Integrated Circuits (RFIC) Symposium, 2005. Digest of Papers. 2005 IEEE, pp. 313 - 316, June 2005
  2. D. Kehrer, and H.D. Wohlmuth and H. Knapp and M. Wurzer and A.L. Scholtz, '40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS' ISSCC, Digest of Technical Papers, pp.344-345, 2003
  3. Tomas H. LEE, 'The Design of CMOS Radio Frequency Integrated Circuits', 2nd, Cambridge University Press, 1998
  4. R. Farjad-Rad et al, 'A 0.4 um CMOS 10-Gb/s 4-PAM pre-emphasis serial link,', IEEE Journal of Solid-state Circuits, vol. 34, pp. 580-585, May 1999 https://doi.org/10.1109/4.760366
  5. R. Farjad-Rad et al, 'A 0.3$\mu$m CMOS 8-Gb/s 4-PAM Serial Link Transceiver', IEEE Journal of Solid-state Circuits, vol. 35, pp. 757-763, May 2000 https://doi.org/10.1109/4.841504
  6. Jean Jiang and Fei Yuan, 'A New CMOS Current-Mode Multiplexer for 10 Gb/s Serial Links', AICSP , vol. 44, pp. 61-76, 2005 https://doi.org/10.1007/s10470-005-1615-0
  7. K. Farzan and David A. Johns, 'A CMOS 7-Gb/s Power-Efficient 4-PAM Transmitter', ESSCIRC, pp. 235-238, 2002
  8. C. K. K. Yang, 'A multi-Gb/s transceiver in CMOS technology', Ph.D. dissertation, Stanford University, 1998
  9. Jri Lee, 'High-speed circuit designs for transmitters in broadb and data links' IEEE Journal, Solid-State Circuits, vol. 41, no. 5, pp.1004-1015, May 2006 https://doi.org/10.1109/JSSC.2006.872871
  10. Behzad Razavi, 'Design of Integrated Circuits for Optical Communications', McGraw-Hill, 2003
  11. R. Jacob Baker, 'CMOS circuit design, layout, and simulation', Wiley Interscience, 2005