Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
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Branch Prediction Latency Hiding Scheme using Branch Pre-Prediction and Modified BTB

분기 선예측과 개선된 BTB 구조를 사용한 분기 예측 지연시간 은폐 기법

  • 김주환 (영남대학교 전자정보공학부) ;
  • 곽종욱 (영남대학교 전자정보공학부) ;
  • 전주식 (서울대학교 전기컴퓨터공학부)
  • Published : 2009.10.31
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Abstract

Precise branch predictor has a profound impact on system performance in modern processor architectures. Recent works show that prediction latency as well as prediction accuracy has a critical impact on overall system performance as well. However, prediction latency tends to be overlooked. In this paper, we propose Branch Pre-Prediction policy to tolerate branch prediction latency. The proposed solution allows that branch predictor can proceed its prediction without any information from the fetch engine, separating the prediction engine from fetch stage. In addition, we propose newly modified BTE structure to support our solution. The simulation result shows that proposed solution can hide most prediction latency with still providing the same level of prediction accuracy. Furthermore, the proposed solution shows even better performance than the ideal case, that is the predictor which always takes a single cycle prediction latency. In our experiments, IPC improvement is up to 11.92% and 5.15% in average, compared to conventional predictor system.

현대의 프로세서 아키텍처에서 정확한 분기 예측은 시스템의 성능에 지대한 영향을 끼친다. 최근의 연구들은 예측 정확도뿐만 아니라, 예측 지연시간 또한 성능에 막대한 영향을 끼친다는 것을 보여준다. 하지만, 예측 지연시간은 간과되는 경향이 있다. 본 논문에서는 분기 예측지연시간을 극복하기 위한 분기 선예측 기법을 제안한다. 이 기법은 분기장치를 인출 단계에서 분리함으로써, 분기 예측기가 명령어 인출 장치로부터의 아무런 정보도 없이 스스로 분기 예측을 진행 가능하게 한다. 또한, 제안된 기법을 지원하기 위해, BTB의 구조를 새롭게 개선하였다. 실험 결과는 제안된 기법이 동일한수준의 분기 예측정확도를 유지하면서, 대부분의 예측지연시간을 은폐한다는 것을 보여준다. 더욱이 제안된 기법은 항상 1 싸이클의 예측 지연시간을 가지는 이상적인 분기 예측기를 사용한 경우보다도 더 나은 성능을 보여준다. 본 논문의 실험 결과에 따르면, 기존의 방식과 비교했을 때, 최대 11.92% 평균 5.15%의 IPC 향상을 가져온다.

Keywords

References

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