ETRI Journal
- Volume 30 Issue 5
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- Pages.707-717
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- 2008
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- 1225-6463(pISSN)
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- 2233-7326(eISSN)
High-Speed Hardware Architectures for ARIA with Composite Field Arithmetic and Area-Throughput Trade-Offs
- Lee, Sang-Woo (S/W & Content Research Laboratory, ETRI) ;
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Moon, Sang-Jae
(Department of Electrical Engineering, Kyungpook National University) ;
- Kim, Jeong-Nyeo (S/W & Content Research Laboratory, ETRI)
- Received : 2008.04.01
- Accepted : 2008.08.22
- Published : 2008.10.31
Abstract
This paper presents two types of high-speed hardware architectures for the block cipher ARIA. First, the loop architectures for feedback modes are presented. Area-throughput trade-offs are evaluated depending on the S-box implementation by using look-up tables or combinational logic which involves composite field arithmetic. The sub-pipelined architectures for non-feedback modes are also described. With loop unrolling, inner and outer round pipelining techniques, and S-box implementation using composite field arithmetic over