Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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TLP Properties Evaluation of ESD Protection Device of GGNMOS Type for Conventional CMOS Process

Conventional CMOS 공정을 위한 GGNMOS Type의 ESD 보호소자의 TLP 특성 평가

  • 이태일 (청주대학교 전자공학과) ;
  • 김홍배 (청주대학교 전자정보공학부)
  • Published : 2008.10.01
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Abstract

In this paper, we deal with the TLP evaluation results for GGNMOS in ESD protection device of conventional CMOS process. An evaluation parameter for GGNMOS is that repeatability evaluation for reference device($W/L=50\;{\mu}m1.0\;{\mu}m$) and following factors for design as gate width, number of finger, present or not for N+ gurad -ring, space of N-field region to contact and present or not for NLDD layer. The result of repeatability was showed uniformity of lower than 1 %. The result for design factor evaluation was ; 1) gate width leading to increase It2, 2) An increase o( finger number was raised current capability(It2), and 3) present of N+ gurad-ring was more effective than not them for current sink. Finally we suggest the optimized design conditions for GGNMOS in evaluated factor as ESD protection device of conventional CMOS process.

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References

  1. J. K. Keller, "Protection of MOS integrated circuits from destruction by electrostatic discharge", EOS/ESD Symposium Proc., 1980
  2. B. K. Joung, J. W. Kang, H. J. Hwang, S. Y. Kim, and O. K. Kwon, "Trade-off characteristic between gate length margin and hot carrier lifetime by considering ESD on NMOSFETs of submicron technology", Trans. EEM, Vol. 7, No. 1, p. 1, 2006 https://doi.org/10.4313/TEEM.2006.7.1.001
  3. 정민철, 윤지영, 유장우, 성만영, "ESD 보호를 위한 LVTSCR의 래치업 차폐회로", 한국전기전자재료학회 2005하계학술대회논문집, p. 178, 2005
  4. S. Dabral and T. Maloney, "Basic ESD and I/O Design", John Wiley & Sons, Inc., p. 16, 1998
  5. Steven H. Voldman, "ESD Physics and Devices", John Wiley & Sons, Ltd., p. 7, 2005
  6. T. Smdes, R. M. D. A. Velghe, R. S. Ruth, and A. J. Huitsing, "The application of transmission line pulse testing for the ESD analysis of integrated circuits", Journal of Electrostatics 56, p. 399, 2002 https://doi.org/10.1016/S0304-3886(02)00057-8
  7. A. Stricker, D. Gloor, and W. Fichtner, "Layer optimization of an ESD protection n- MOSFET by simulation and measurement", in Proc. EOS/ESD Symp., p. 205, 1995
  8. Stephen G. Beebe, "Characterization, Modeling, and Design of ESD Protection Circuits", Technical report, Advanced micro devices, Sunnyvale, California, 1998