Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

The Design of a Low Power and Wide Swing Charge Pump Circuit for Phase Locked Loop

넓은 출력 전압 범위를 갖는 위상동기루프를 위한 저전압 Charge Pump 회로 설계

  • Pu, Young-Gun (Department of Electronic Engineering, Konkuk University) ;
  • Ko, Dong-Hyun (Department of Electronic Engineering, Konkuk University) ;
  • Kim, Sang-Woo (Department of Electronic Engineering, Konkuk University) ;
  • Park, Joon-Sung (Department of Electronic Engineering, Konkuk University) ;
  • Lee, Kang-Yoon (Department of Electronic Engineering, Konkuk University)
  • 부영건 (건국대학교 전자정보통신공학부) ;
  • 고동현 (건국대학교 전자정보통신공학부) ;
  • 김상우 (건국대학교 전자정보통신공학부) ;
  • 박준성 (건국대학교 전자정보통신공학부) ;
  • 이강윤 (건국대학교 전자정보통신공학부)
  • Published : 2008.08.25
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a new circuit is proposed to minimize the charging and discharging current mismatch in charge pump for UWB PLL application. By adding a common-gate and a common-source amplifier and building the feedback voltage regulator, the high driving charge pump currents are accomplished. The proposed circuit has a wide operation voltage range, which ensures its good performance under the low power supply. The circuit has been implemented in an IBM 0.13um CMOS technology with 1.2V power supply. To evaluate the design effectiveness, some comparisons have been conducted against other circuits in the literature.

본 논문에서는 UWB PLL charge pump 의 충/방전 전류오차를 최소화하기 위한 회로를 제안하였다. Common-gate 와 Common-source 증폭기를 추가한 피드백 전압 조정기를 구성하여 높은 응답성을 가지는 charge pump를 설계하였다. 제안한 회로는 넓은 동작 영역을 갖으며, 낮은 전원 전압으로도 뛰어난 성능을 보인다. 본 회로는 1.2V 공급 전압과 IBM 0.13um CMOS 공정으로 집적되었다. 설계의 효율성을 평가하기 위해 참고 논문의 다른 회로와 성능을 대조하였다.

Keywords

References

  1. Y. S. Choi and D. H. Han, "Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop", IEEE Trans. on Circuits and Systems-II Express Briefs, Vol.53, No. 10, October 2006. pp. 1022-1025 https://doi.org/10.1109/TCSII.2006.882122
  2. J. S. Lee and M. S. Keel, S. Lim and S. Kim, "Charge Pump with Perfect Current Matching Characteristics in Phase-Locked Loop", Electronics Letters, Vol. 36, No.23, November 2000, pp. 1907-1908 https://doi.org/10.1049/el:20001358
  3. B. Bahreyni and I. M. Filanovsky, "A 2.5-10-GHz Clock Multiplier Unit with 0.22ps RMS Jitter in Standard 0.18um CMOS", IEEE J. Solid State Circuits, Vol.39, No.11, pp. 1862-1872, November 2004 https://doi.org/10.1109/JSSC.2004.835833
  4. S. F. Cheng, H. T. Tong, J. S. Martinez, A. I. Karsilayan, "Design and Analysis of an Ultrahigh- Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching", IEEE Trans. on Circuits and Systems-II Express Briefs, Vol.53, No. 9, September 2006, pp. 843-847 https://doi.org/10.1109/TCSII.2006.879100
  5. B. Terlemez and J.P.Uyemura, "The Design of a Differential CMOS Charge Pump for High Performance Phase-Locked Loops", Proc. IEEE International Symposium on Circuit and Systems (ISCAS), 2004
  6. K. S. Ha and L. S. Kim, "Charge-Pump Reducing Current Mismatch in DLLs and PLLs", Proc. IEEE International Symposium on Circuit and Systems (ISCAS), 2006
  7. P. E. Allen and D. R. Holberg, "CMOS Analog Circuit Design-second edition", Oxford University Press, 2002