References
- Allan, G. A. and Walton, A. J. (1997), Efficient critical area estimation for arbitrary defect shapes, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 20-28
- Barnett, T. S. and Singh, A. D. (2003), Extracting integrated-circuit yieldmodels to estimate early-life reliability, IEEE Transactions on Reliability, 52(3), 296-300 https://doi.org/10.1109/TR.2003.816418
- Cunningham, J. A. (1990), The use of evaluation of yield models in integrated circuit manufacturing, IEEE Transactions on Semiconductor Engineering, 3(2), 60-71 https://doi.org/10.1109/66.53188
- Ha, C. (2004), Reliability-yield allocation for semiconductor integrated circuits: modeling and optimization, Ph.D. dissertation, Texas A&M University
- Ha, C. (2007), Relationship between yield and cost considering repair and rework for LCD manufacturing system, Journal of the Korean Institute of Industrial Egineers, accepted
- Hansen, C. K. and Thyregod, P. (1996), Modeling and estimation of wafer yields and defect densities from micro electronics test structure data, Quality and Reliability Engineering International, 12, 9-17 https://doi.org/10.1002/(SICI)1099-1638(199601)12:1<9::AID-QRE975>3.0.CO;2-K
- Hwang, J. Y., Kuo, Way, and Ha, C. (2007), Modeling of integrated circuit yield using a spatial nonhomogeneous Poisson process, Naval Research Logistics, to be submitted
- Izenman, A. J. (1991), Recent developments in nonparametric density estimation, Journal of the American Statistical Association, 86(413), 205-224 https://doi.org/10.2307/2289732
- Kikuda, S., Miyamoto, H., Mori, S., Niiro, M., and Yamada, M. (1991), Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and 126 beyond, IEEE Journal of Solid-State Circuits, 26(11), 1550-1555 https://doi.org/10.1109/4.98971
- Koren, I. and Koren, Z. (1998), Defect tolerance in VLSI circuits : Techniques and yield analysis, Proceedings of the IEEE, 86(9), 1819-1837
- Li, J. F., Yeh, J. C., Huang, R. F., and Wu, C. W. (2005), A built-in self-repair design for rams with 2-d redundancy, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(6), 742-745 https://doi.org/10.1109/TVLSI.2005.848824
- Milor, L. S. (1999), Yield modeling based on in-line scanner defect sizing and a circuit's critical area, IEEE Transactions on Semiconductor Manufacturing, 12(1), 26-35 https://doi.org/10.1109/66.744517
- Shindo, W., Nurani, R. K., and Strojwas, A. J. (1998), Effects of defect propagation/ growth on inline defect-based yield prediction, IEEE Transactions on Semiconductor Manufacturing, 11(4), 546-551 https://doi.org/10.1109/66.728550
- Stapper, C. H. (1973), Defect density distribution for LSI yield calculation, IEEE Transactions on Electron Devices, ED-20, 655-657
- Stapper, C. H. (1984), Modeling of defects in integrated circuit photolithographic patterns, IBM Journal of Research and Development, 28(4), 461-475 https://doi.org/10.1147/rd.284.0461
- Stapper, C. H. (1993), Improved yield models for fault-tolerant memory chips, IEEE Transactions on Computers, 42(7), 872-881 https://doi.org/10.1109/12.237727
- Stapper, C. H. and Rosner, R. J. (1995), Integrated circuit yield management and yield analysis: development and implementation, IEEE Transactions on Semiconductor Manufacturing, 8(2), 95-102 https://doi.org/10.1109/66.388016
- Way Kuo, Chien, W. K. and Kim, T. (1998), Reliability, Yield, and Stress Burn-in: A Unified Approach for Microelectronics Systems Manufacturing and Software Development, Norwell, Kluwer Academic Publishers
- Yoo, J. H., Kim, K. C., Lee, K. C., and Kyung, K. H. (1996), A 32-Bank 1Gb self-strobing synchronous DRAM with 1 Gbyte/s bandwidth, IEEE Journal of Solid-State Circuits, 31(11), 1635-1644 https://doi.org/10.1109/JSSC.1996.542308
- Zhou, C., Ross, R., Vickery, C., Metteer, B., Gross, S., and Verret, D. (2002), Yield prediction using critical area analysis with inline defect data, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 82-86