Journal of the Korea Institute of Information and Communication Engineering (한국정보통신학회논문지)

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A design of Giga-bit security module using Fully pipe-lined CTR-AES

Full-pipelined CTR-AES를 이용한 Giga-bit 보안모듈 설계

  • ;
  • 박주현 (전남대학교 컴퓨터정보통신학과) ;
  • 김영철 (전남대학교 컴퓨터정보통신학과) ;
  • 김광옥 (한국전자통신연구원)
  • Published : 2008.06.30
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Abstract

Nowdays, homes and small businesses rely more and more PON(Passive Optical Networks) for financial transactions, private communications and even telemedicine. Thus, encryption for these data transactions is very essential due to the multicast nature of the PON In this parer, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features; 1) Composite field arithmetic SubByte, 2) efficient MixColumn transformation 3) and on-the-fly key-scheduling for fully pipelined architecture. By pipeling the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the on-the-fly key-scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.

현재 가정과 소규모 사업장에서 재정적인 변화와 개인 커뮤니케이션 그리고 원격의료에 이르기까지 점점 GPON 사용이 일반화 되어가고 있다. 이러한 PON의 다중사용 때문에 개인정보 보호와 커뮤니케이션 보호를 위한 보안의 필요성이 더더욱 커지고 있다. 이를 위해 이 논문에서는 Virtex4 FPGA를 기반으로 AES의 카운터 모드를 구현하였다. 본 논문에서 구현된 구조는 pipeline 구조 구현을 위하여 크게 세 가지 특징을 가지고 있는데 1) composite filed 연산을 이용한 Subbyte, 2) efficient MixColumn transformation, 그리고 3) on-the-fly key scheduling이다. 구현된 S-box는 면적의 17% 감소와 on-the-fly key 스케줄링 기법으로 pipeline 구조에 특화된 key-expander 기능을 구현하였다.

Keywords

References

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