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Damage Effect and Delay Time of CMOS Integrated Circuits Device with Coupling Caused by High Power Microwave

도선에 커플링 되는 고출력 전자파에 의한 CMOS IC의 피해 효과 및 회복 시간

  • Published : 2008.06.30

Abstract

This paper examines the damage effect and delay time of CMOS integrated circuits device with coupling caused by high power microwaves. The waveguide and magnetron was employed to study the influence of high power micro-waves on CMOS inverters. The CMOS inverters were composed of a LED circuit for visual discernment. Also CMOS inverters broken by high power microwave is observed with supply current and delay time. When the power supply current was increased 2.14 times for normal current at 9.9 kV/m, the CMOS inverter was broken by latch-up. Three different types of damage were observed by microscopic analysis: component, onchipwire, and bondwire destruction. Based on the results, CMOS inverters can be applied to database to elucidate the effects of microwaves on electronic equipment.

본 논문은 고출력 전자파에 따른 CMOS IC 소자의 피해 효과와 회복 시간을 알아보았다. 고출력 전자파 발생 장치는 마그네트론을 사용하였고, CMOS 인버터의 오동작/부동작 판별법은 유관 식별이 가능한 LED 회로로 구성하였다. 그리고 고출력 전자파에 의해 오동작된 CMOS 인버터의 전원 전류와 회복 시간을 관찰하였다. 그 결과, 전계 강도가 약 9.9 kV/m에서의 전원 전류는 정상 전류의 2.14배가 증가하였다. 이는 래치업에 의한 CMOS 인버터가 오작동된 것을 확인할 수 있었다. 또한, COMS 인버터의 파괴는 컴포넌트, 온칩와이어, 그리고 본딩 와이어에서 다른 형태로 관찰하였다 위 실험 결과로, 전자 장비의 고출력 전자파 장해에 대한 이해를 돕는데 기초 자료로 활용될 것으로 예측된다.

Keywords

References

  1. Mats G. Backstrom, "Susceptibility of electronic systems to high power microwaves: Summary of test experience", IEEE Transactions on Electromagnetic Compatibility, vol. 46, no. 3, Aug. 2004
  2. Mats G. Backstrom, "The threat from intentional EMI against the civil technical infrastructure", Reprint from ESW2006, 3rd European Survivability Workshop, pp. 16-19, May 2006
  3. D. Taylor, D. V. Giri, High-power Microwave Systems and Effects, Washington, D.C., Taylor & Francis, 1994
  4. M. Camp, H. Garbe, and D. Nitsch, "Influence of the technology on the destruction effects of semi-conducters by impact of EMP and UWB pulses", IEEE Trans. on EMC, vol. 1, pp. 87-92, 2002
  5. "JESD78 latch-up testing standard", Electronic Industry Association JEDEC standards, Arlington, VA.
  6. M. Camp, H. Gerth, H. Garbe, and H. Haase, "Predicting the breakdown behavior of microcontrollers under EMP/UWB impact using a statistical analysis", IEEE Trans. on Electromagnetic Compatibility, vol. 46, pp. 368-379, 2004 https://doi.org/10.1109/TEMC.2004.831816
  7. D. B. Estreich, "The physics and modeling of latch- up and CMOS integrated circuits", Stanford Electron. Labs., Stanford, CA, Tech. Rep. G201-9, Nov. 1980
  8. J. E. Hall, J. A. Seitchik, L. A. Arledge, P. Yang, and P. K. Fung, "Analysis of latchup susceptibility in CMOS circuits", Electron Devices Meeting, 1984 International, vol. 30, pp. 292-295, 1984

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