An Analytical Model for Deriving The Threshold Voltage Expression of A Short-gate Length SOI MESFET

Short-gate SOI MESFET의 문턱 전압 표현 식 도출을 위한 해석적 모델

  • Kal, Jin-Ha (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Suh, Chung-Ha (School of Electronic & Electrical Eng., Hongik Univ.)
  • 갈진하 (홍익대학교 전자전기공학부) ;
  • 서정하 (홍익대학교 전자전기공학부)
  • Published : 2008.07.25

Abstract

In this paper, a simple analytical model for deriving the threshold voltage of a short-gate SOI MESFET is suggested. Using the iteration method, the Poisson equation in the fully depleted silicon channel and the Laplace equation in the buried oxide region are solved two-dimensionally, Obtained potential distributions in each region are expressed in terms of fifth-order of $\chi$, where $\chi$ denotes the coordinate perpendicular to the silicon channel direction. From them, the bottom channel potential is used to describe the threshold voltage in a closed-form. Simulation results show the dependencies of the threshold voltage on the various device geometry parameters and applied bias voltages.

본 논문에서는 short-gate SOI MESFET의 문턱전압 도출을 위한 간단한 해석적 모델을 제시하였다. 완전 공핍된 실리콘 채널 영역에서는 2차원 Poisson 방정식을, buried oxide 영역에서는 2차원 Laplace 방정식을 반복법(iteration method)을 이용해 풀어 각 영역 내에서의 전위 분포를 채널에 수직한 방향의 좌표에 대해 5차 다항식으로 표현하였으며 채널 바닥 전위를 구하였다. 채널 바닥 전위의 최소치가 0이 되는 게이트 전압을 문턱 전압으로 제안하여 closed-form의 문턱 전압 식을 도출하였다. 도출된 문턱 전압 표현 식을 모의 실험한 결과, 소자의 구조 parameter와 가해진 bias 전압에 대한 정확한 의존성을 확인할 수 있었다.

Keywords

References

  1. J. D. Marshall and J. D. Meindl, 'A sub- and near-threshold current model for silicon MESFETs,' IEEE Trans. Electron Devices, vol. ED-35, pp. 388-390, Mar 1988
  2. Q. Chen, M. Willander, J. Charter, C. H. Thaki, and E. R. A. Evans, 'Fabrication and performances of delta-doped Si n-MESFET grown by MBE,' Electron. Lett., vol. 29, pp. 671-673, Apr 1993 https://doi.org/10.1049/el:19930450
  3. A. Georagkilas, G. Halkias, A. Christou, C. Papavassiliou, G. Perantinus, G. Konstantinidis, and P. Panayotatos, 'Microwave performance of GaAs-on-Si MESFETs with Si buffer layers,' IEEE Trans. Electron Devices, vol. 40, pp. 507-512, Mar 1993 https://doi.org/10.1109/16.199355
  4. C. D. Hartgring, B. A. Rosario, and J. M. Pickett, 'Silicon MESFET digital circuit techniques,' IEEE J. Solid-State Circuits, vol. 16, pp. 578-584, May 1981 https://doi.org/10.1109/JSSC.1981.1051640
  5. K. P. MacWiliams and J. D. Plummer, 'Device physics and technology of complementary silicon MESFETs for VLSI applications,' IEEE Trans. Electron Devices, vol. 38, pp. 2619-2631, Dec 1991 https://doi.org/10.1109/16.158684
  6. J. Nulman, J. V. Faricelli, J. P. Krusius, and J. Frey, 'Fabrication and analysis of (1=2)m silicon logic MESFETs,' IEEE Trans. Electron Devices, vol. ED-30, pp. 1395-1401, Oct 1983
  7. U. Magnusson, J. Tiren, A. Soderbarg, M. Rosling, O. Grelsson, H. Bleichner, J. O. Nylander, and S. Berg, 'Bulk silicon technology for complementary MESFETs,' Electron. Lett., vol. 25, pp. 565-566, 1989 https://doi.org/10.1049/el:19890385
  8. G. V. Ram and M. I. Elmasry, 'On the scaling of Si-MESFETs,' IEEE Electron Device Lett., vol. EDL-1, pp. 259-262, Dec 1980
  9. P. A. Tove, K. Bohlin, F. Masszi, H. Norde, J. Nylander, J. Tiren, and U. Magnusson, 'Complementary Si-MESFET concept using silicon-on-sapphire technology,' IEEE Electron Device Lett., vol. EDL-9, pp. 47-49, Jan 1988
  10. G.Bert et al., 'Femto Joule logic circuits using normally of GaAs MESFET,' Electron Lett., vol 13, pp. 644, 1977 https://doi.org/10.1049/el:19770459
  11. MEDICI Two Dimensional Device Simulation Program, Version 2002. 4, User Manual. Avantcorporation, TCAD Business Unit
  12. ATLAS User's Manual, vols. 1-2, software version 6.5.0.R, Silvaco International
  13. T. K .Chiang, Y. H. Wang, and M. P. Houng, 'Modeling of threshold voltage and sub-threshold swing of short-channel SOI MESFET's,' Solid-State Electron, vol. 43, pp. 123-129, 1999 https://doi.org/10.1016/S0038-1101(98)00240-8
  14. Vivek K. De, James D. Meindl, 'An Analytical Threshold Voltage and Subthreshold Current Model for Short-Channel MESFET's,' IEEE J. Solid-State Circuits, vol. 28(2), pp. 169-172, 1993 https://doi.org/10.1109/4.192050
  15. J. G. Cao, 'A Simplified 2-D Analytic model for the threshold Voltage of fully depleted short gate-length Si-SOI MESFETs,' IEEE Trans. Electron Devices, vol. 43, pp. 2156-2162, 1995
  16. S. P. Chin, C. Y. Wu, 'A New Two-Dimensional Model for the Potential Distribution of Short Gate-Length MESFET's and its Applications,' IEEE Trans. Electron Devices, vol. 39, pp. 1928-1937, 1992 https://doi.org/10.1109/16.144686
  17. C. S. Hou, C. Y. Wu, 'A 2D Analytic Model for the Threshold-Voltage of Fully Depleted Short Gate-Length Si-SOI MESFET's,' IEEE Trans. Electron Devices, vol. 42, pp. 2156-2161, 1995. https://doi.org/10.1109/16.477774
  18. Prashant Pandey, B. B. Pal, and S. Jit, 'A New 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Si-SOI MESFETs,' IEEE Trans. Electron Devices, vol. 51, pp. 246-254, 2004 https://doi.org/10.1109/TED.2003.822225