한국재료학회지 (Korean Journal of Materials Research)

  • 제18권5호
  • /
  • Pages.272-276
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  • 2008
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  • 1225-0562(pISSN)
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  • 2287-7258(eISSN)
한국재료학회 (Materials Research Society of Korea)
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[ 0.1\;μm ] SOI-MOSFET의 적정 채널도핑농도에 관한 시뮬레이션 연구

Investigation of Optimal Channel Doping Concentration for 0.1\;μm SOI-MOSFET by Process and Device Simulation

  • 최광수 (수원대학교 공과대학 전자재료공학과)
  • Choe, Kwang-Su (Dept. of Electronic Materials Engineering, College of Engineering University of Suwon)
  • 발행 : 2008.05.27
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초록

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

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참고문헌

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