고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems

  • 발행 : 2008.03.25

초록

본 논문에서는 TFT-LCD 디스플레이 및 디지털 TV 시스템 응용과 같이 고속으로 동작하며 고해상도, 저전력 및 소면적을 동시에 요구하는 고화질 영상시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC를 제안한다. 제안하는 ADC는 3단 파이프라인 구조를 사용하여 고해상도와 높은 신호처리 속도에서 전력 소모 및 면적을 최적화하였다. 입력단 SHA 회로에는 Nyquist 입력에서도 12비트 이상의 정확도로 신호를 샘플링하기 위해 게이트-부트스트래핑 회로를 적용함과 동시에 트랜스컨덕턴스 비율을 적절히 조정한 2단 증폭기를 사용하여 12비트에 필요한 높은 DC 전압 이득과 충분한 위상 여유를 갖도록 하였으며, MDAC의 커패시터 열에는 높은 소자 매칭을 얻기 위하여 각각의 커패시터 주위를 공정에서 제공하는 모든 금속선으로 둘러싸는 3차원 완전 대칭 구조를 갖는 레이아웃 기법을 적용하였다. 한편, 제안하는 ADC에는 전원 전압 및 온도에 덜 민감한 저전력 기준 전류 및 전압 발생기를 온-칩으로 집적하여 잡음을 최소화하면서 시스템 응용에 따라 선택적으로 다른 크기의 기준 전압 값을 외부에서 인가할 수 있도록 하였다. 제안하는 시제품 ADC는 0.18um n-well 1P6M CMOS 공정으로 제작되었으며, 측정된 DNL 및 INL은 12비트 해상도에서 각각 최대 0.69LSB, 2.12LSB의 수준을 보이며, 동적 성능으로는 120MS/s와 130MS/s의 동작 속도에서 각각 최대 53dB, 51dB의 SNDR과 68dB, 66dB의 SFDR을 보여준다. 시제품 ADC의 칩 면적은 $1.8mm^2$이며 전력 소모는 1.8V 전원 전압과 130MS/s에서 108mW이다.

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

키워드

참고문헌

  1. K. Nair and R. Harjani, "A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 456-539
  2. S. Mathur, M. Das, P. Tadeparthy, S. Ray, S. Mukherjee, and B. L. Dinakaran, "A 115mW 12-bit 50MSPS pipelined ADC," in Proc. ISCAS, May 2002, pp. 913-916
  3. H. Pan, M. Segami, M. Choi, J. Cao, and A. Abidi, "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1769-1780, Dec. 2000 https://doi.org/10.1109/4.890290
  4. J. Yuan, N. Farhat, and I. Van der Spiegel, "A 50MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration," in Proc. IEEE CICC, Sept. 2005, pp. 399-402
  5. A. Shabra and Hae-Seung Lee, "A 12-bit mismatch-shaped pipeline A/D converter," in Symp. VLSI Circuits Dig. Tech. Papers, June 2001. pp. 211-214
  6. H. Ploeg, G. Hoogzaad, H. Termeer, M. Vertregt, and R. Roovers, "A 2.5V 12b 54MSamples/s 0.25um CMOS ADC in $1mm^2$ with mixed-signal chopping and calibration," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1859-1867, Dec. 2001 https://doi.org/10.1109/4.972136
  7. A. Shabra and Hae-Seung Lee, "Oversampled pipeline A/D converters with mismatch shaping," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 566-578, May 2002 https://doi.org/10.1109/4.997849
  8. L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz," in ISSCC Dig. Tech. Papers, Feb. 2000, pp. 38-39
  9. E. Iroaga and B. Murmann, "A 12b, 75MS/s pipelined ADC using incomplete settling," in Symp. VLSI Circuits Dig. Tech. Papers, June 2006, pp. 274-275
  10. B. Murmann and B. E. Boser, "A 12b 75MS/s pipelined ADC using oper-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003 https://doi.org/10.1109/JSSC.2003.819167
  11. A. Zjajo, H. Ploeg, and M. Vertregt, "A 1.8V 100mW 12bits 80Msample/s Two-Step ADC in 0.18-um CMOS," in Proc. ESSCIRC, Sept. 2003, pp. 241-244
  12. C. R. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038-1046, May 2005 https://doi.org/10.1109/JSSC.2005.845972
  13. H. Wang, C. F. Chan, and C. S. Choy, "A 12-bit 80MS/s 110mW Floating Analog-to-Digital Converter," in Proc. ISCAS, May 2002, pp. 137-140
  14. T. Ito, D. Kurose, T. Ueno, T. Yamaji, and T. Itakura, "55mW 1.2V 12bit 100-MSPS pipeline ADCs for wireless receivers," in Proc. ESSCIRC, Sept. 2006, pp. 540-543
  15. T. N. Andersen et al., "A cost-efficient high-speed 12-bit pipeline ADC in 0.18um digital CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1506-1513, July 2005 https://doi.org/10.1109/JSSC.2005.847519
  16. S. M. Yoo, T. H. Oh, H. Y. Lee, K. H. Moon, and J. W. Kim, "A 3.0V 12b 120 MSample/s CMOS pipelined ADC," in Proc. ISCAS, May 2006, pp. 1023-1026
  17. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipelined analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999 https://doi.org/10.1109/4.760369
  18. Y. J. Cho, K. H. Lee, H. C. Choi, S. H Lee, K. H. Moon, and J. W. Kim, "A calibration-free 14b 70MS/s $3.3mm^2$ 235mW 0.13um CMOS pipeline ADC with high-matching 3-D symmeric capacitors," in Proc. IEEE CICC, Sept. 2006, pp. 485-488
  19. S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, "A 2.5 V 10b 120MSample/s CMOS pipelined ADC with high SFDR," in Proc. IEEE CICC, May 2002, pp. 441-444
  20. K. N. Leung and P. K. T. Mok, "A sub-1-V $15ppm/^{\circ}C$ CMOS bandgap voltage reference without requiring low threshold voltage device," IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 526-530, Apr. 2002 https://doi.org/10.1109/4.991391
  21. A. E. Buck, C. L. McDonald, S. H. Lewis, and T. R Viswanathan, "A CMOS bandgap reference without resistors," IEEE J. Solid-State Circuits, vol. 37, no. 1, pp. 81-83, Jan. 2002 https://doi.org/10.1109/4.974548
  22. S. H Lee and Y. Jee, "A Temperature and Supply-Voltage Insensitive CMOS Current Reference," IEICE Trans. Electron, vol. E82-C, no. 8, pp. 1562-1566, Aug. 1999
  23. Y. J. Cho and S. H. Lee, "An 11b 70-MHz $1.2-mm^2$ 49-mW 0.18-um CMOS ADC with on-chip current/voltage references," IEEE Transactions on Circuit and Systems I, vol. 52, no. 10, pp. 1989-1995, Oct. 2005 https://doi.org/10.1109/TCSI.2005.853251