대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

WCDMA 통신용 I-Q 채널 12비트 1GS/s CMOS DAC

I-Q Channel 12bit 1GS/s CMOS DAC for WCDMA

  • Seo, Sung-Uk (Dept. of Electronic Engineering, Inha University) ;
  • Shin, Sun-Hwa (Dept. of Electronic Engineering, Inha University) ;
  • Joo, Chan-Yang (Dept. of Electronic Engineering, Inha University) ;
  • Kim, Soo-Jae (Dept. of Electronic Engineering, Inha University) ;
  • Yoon, Kwang-S. (Dept. of Electronic Engineering, Inha University)
  • 발행 : 2008.01.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 WCDMA 통신용 송신기에 적용 가능한 12비트 1GS/s 전류구동 방식의 혼합형 DAC를 설계하였다. 제안된 DAC는 혼합형 구조로써 하위 4비트는 이진 가중치 구조, 중간비트와 상위비트는 4비트 온도계 디코더 구조로 12비트를 구성하였다. 제안된 DAC는 혼합형 구조에서 발생되는 지연시간에 따른 성능 저하를 개선하기 위해 지연시간보정 회로를 사용하였다. 지연시간보정 회로는 위상주파수 검출기, 전하펌프, 제어회로로 구성되어 이진 가중치 구조와 온도계 디코더 구조에서 발생하는 지연시간을 감소시킨다. 제안한 DAC는 CMOS $0.18{\mu}m$ 1-poly 6-metal n-well 공정을 사용하여 제작되었고 측정된 INL/DNL은 ${\pm}0.93LS/$ 0.62LSB 이하로 나타났다. 입력 주파수 1MHz에서 SFDR은 약 60dB로 측정되었고 SNDR은 51dB로 측정되었다. 단일 DAC의 전력소모는 46.2mW로 나타났다.

This paper describes a 12 bit 1GS/s current mode segmented DAC for WCDMA communication. The proposed circuit in this paper employes segmented structure which consists of 4bit binary weighted structure in the LSB and 4bit thermometer decoder structure in the mSB and MSB. The proposed DAC uses delay time compensation circuits in order to suppress performance decline by delay time in segmented structure. The delay time compensation circuit comprises of phase frequency detector, charge pump, and control circuits, so that suppress delay time by binary weighted structure and thermometer decoder structure. The proposed DAC uses CMOS $0.18{\mu}m$ 1-poly 6-metal n-well process, and measured INL/DNL are below ${\pm}0.93LSB/{\pm}0.62LSB$. SFDR is approximately 60dB and SNDR is 51dB at 1MHz input frequency. Single DAC's power consumption is 46.2mW.

키워드

참고문헌

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