참고문헌
- M. Loghiy, F. Angiolini, D. Bertozzi, and L. Benini, "Analyzing on-chip communication in a MPSoC Environment," in Proc. Design Automation and Test in Europe, pp. 752-757, Feb. 2004
- Niagara 2 Opens the Floodgates, Microprocessor Report, Nov. 2006
- Advanced AMBA 3 Interconnect IP (PL301), ARM, http://www.arm.com/products/solutions/PL301_AMBA3AXI.html
- K. Lahiri, A. Raghunathan, and S. Dey, "Design space exploration for optimizing on-chip communication architectures," IEEE Transactions on Computer-Aided Design of integrated circuits and systems, Vol.23, No.6, Jun. 2004
- S. Kim and S. Ha, "Efficient exploration of bus-based System-on-Chip architectures," IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol.14, No.7, pp. 681-692, Jul. 2006 https://doi.org/10.1109/TVLSI.2006.878260
- AXI, ARM, http://www.arm.com/products/solutions/ AMBA3AXI.html
- J. Yoo, S. Yoo, and K. Choi, "Communication architecture synthesis of cascaded bus matrix," in Proc. ASP-DAC, pp. 171-177, Jan. 2007
- S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Constraint-driven bus matrix synthesis for MPSoC," in Proc. Asia and South Pacific Design Automation Conference, pp. 30-35, Jan. 2006
- O. Ogawa, S. Bayon de Noyer, P. Chauvet, K. Shinohara, Y. Watanabe, H. Niizuma, T. Sasaki, and Y. Takai, "A practical approach for bus architecture optimization at transaction level," in Proc. Design Automation and Test in Europe, pp. 176-181, Mar. 2003
- S. Kim, C. Im, and S. Ha, "Schedule-aware performance estimation of communication architecture for efficient design space exploration," IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol.13, No.5, pp. 539-552, May 2005 https://doi.org/10.1109/TVLSI.2004.842912
- K. Lahiri, A. Raghunathan, and S. Dey, "System- level performance analysis for designing system- on-chip communication architecture," IEEE Transactions on Computer-Aided Design of integrated circuits and systems, Vol.20, pp. 768-783, Jun. 2001 https://doi.org/10.1109/43.924830
- P. V. Knudsen and J. Madsen, "Communication estimation for hardware/software codesign," in Proc. International Workshop on Hardware/Software Codesign, pp. 55-59, Mar. 1998
- P. Knudsen and J. Madsen, "Integrating communication protocol selection with partitioning in hardware/software codesign," in Proc. International Symposium on System Level Synthesis, pp. 111-116, Dec. 1998
- S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, "FABSYN: Floorplan-aware bus architecture synthesis," IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol.14, No.3, pp. 241-253, Mar. 2006 https://doi.org/10.1109/TVLSI.2006.871763
- S. Murali, L. Benini, and G. De Micheli, "An application-specific design methodology for on-chip crossbar generation," IEEE Transactions on Computer-Aided Design of integrated circuits and systems, Vol.26, No.7, pp. 1283-1296, Jul. 2007 https://doi.org/10.1109/TCAD.2006.888284
- E.-G. Jung, J.-G. Lee, S.-H. Kwak, K.-S. Jhang, J.-A Lee, and D.-S. Har, "High performance asynchronous on-chip bus with multiple issue and out-of-order/In-order completion," in Proc. ACM Great Lake Symposium on VLSI, pp. 152-155, Apr. 2005
- S. Lee and S.-C. Park, "Transaction analysis of multiprocessor based platform with bus matrix," in Proc. Workshop on System-on-Chip for Real-Time Applications, pp. 552-556, Jul. 2005
- J. Hu, U. Y. Ogras, and R. Marculescu, "System- level buffer allocation for application-specific Networks-on-Chip router design," IEEE Transactions on Computer-Aided Design of integrated circuits and systems, Vol.25, No.12, pp. 2919-2933, Dec. 2006 https://doi.org/10.1109/TCAD.2006.882474
- L. Kleinrock, "Queueing systems, Volume I: Theory," Wiley Interscience, New York, 1975
- SystemC Language Reference Manual, ver 2.1. (2005, May). http://www.systemc.org/web/sitedocs/ lrm_2_1.html
- G. Varatkar and R. Marculescu, "On-chip traffic modeling and synthesis for mpeg-2 video applications," IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol.12, No.1, pp. 108- 119, Jan. 2004 https://doi.org/10.1109/TVLSI.2003.820523