Information and Communications Magazine (정보와 통신)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
권호 표지

Research Challenges in Many-core SoC Designs

  • Published : 2008.11.25
Download PDF
⟨ Previous Next ⟩

Abstract

본고에서는 최근 학계에서뿐만 아니라 Intel, nVidia 등의 반도체 설계업계에서도 차세대 system-on-chip (SoC) 구조로 제안하고, 실제품 설계까지 진행 중인 many-core SoC의 research challenges를 알아본다. 이러한 challenges는 architecture, software, application의 3가지 면에서 살펴보는데, 각 분야에서 주요 문제들을 고찰하고, 이 문제들을 해결하기 위해 현재 진행 중인 주요 연구 방향들을 살펴보고자 한다.

Keywords

References

  1. Cisco CRS-1 Overview, available at www.cs.ucsd.edu/~varghese/crs1.ppt
  2. S. Vangal, et al., 'An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS' , IEEE Journal of Solid State Circuits.Jan, 2008
  3. nVidia Tesla S1070, http://www.nvidia.com/object/tesla_s1070.html
  4. L. Seiler, et al., 'Larrabee: A Many-Core x86 Architecture for Visual Computing' , ACM Transactions on Graphics, August 2008
  5. S. Borkar, 'Thousand Core Chips - A Technology Perspective' , Proc. Design Automation Conference, June 2007
  6. B. Beckmann and D. Wood, 'TLC: Transmission Line Caches' , Proc, IEEE/ACM International Symposium on Microarchitecture, 2003
  7. C. Kim, D. Burger, and S, Keckler, 'An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches' , Proc, International Conference on Architectural Support for Programming Languages and Operating Systems, 2003
  8. A. Kumar, et al., 'Express virtual channels: towards the ideal interconnection fabric' , Proc. International Symposium on Computer Architecture, 2007
  9. T. Krishna, et al, 'NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication' , Symposium on High Performance Interconnects, Aug. 2008
  10. W. Kwon, et al., 'A Practical Approach of Memory Access Parallelization to Exploit Multiple Off-chip DDR Memories' , Proc, Design Automation Conference, June 2008
  11. Microsoft, SXM: C# Software Transactional Memory, 2005
  12. C. Garcia, et al. 'Mitosis Compiler:An Infrastructure for Speculative Threading Based on Pre-Computation Slices' , Proc. Conference on Programming Language Design and Implementation, 2005
  13. Microsoft Co., 'The Manycore Shift: Microsoft Parallel Computing Initiative Ushers Computing into Next Era' , Microsoft white paper available at www.microsoftcom/presspass/events/supercomputing /docs/ManycoreWP.doc, Nov. 2007
  14. J. Held, J. Bautista, and S. Koehl, 'From a Few Cores to Many' , Intel white paper available at ftp://download.intel.com/research/platform/terascale/t erascale_overview_paper.pdf
  15. P, Dubey, 'Recognition, Mining and Synthesis Moves Computers to the Era of Tera.' Intel Technology Journal, Feb. 2005
  16. Weirong Zhu, et al. 'Exploring Financial Applications on Many-Core-on-a-Chip Architecture: A First Experiment'. Proc, ISPA Workshops 2006