한국전자파학회논문지 (The Journal of Korean Institute of Electromagnetic Engineering and Science)

  • 제19권10호
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  • Pages.1147-1158
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  • 2008
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  • 1226-3133(pISSN)
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  • 2288-226X(eISSN)
한국전자파학회 (The Korean Institute of Electromagnetic Engineering and Science)
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Ku-대역 유전체 공진기 발진기의 Sampling Phase Detector를 이용한 위상 고정 루프 필터 설계 및 제작

Design of Phase Locking Loopfilter Using Sampling Phase Detector for Ku-Band Dielectric Resonator Oscillator

  • Badamgarav, O. (Department of Radio Science and Engineering, Chungnam National University) ;
  • Yang, Seong-Sik (Department of Radio Science and Engineering, Chungnam National University) ;
  • Oh, Hyun-Seok (Department of Radio Science and Engineering, Chungnam National University) ;
  • Lee, Man-Hee (Department of Radio Science and Engineering, Chungnam National University) ;
  • Jeong, Hae-Chang (Department of Radio Science and Engineering, Chungnam National University) ;
  • Yeom, Kyung-Whan (Department of Radio Science and Engineering, Chungnam National University)
  • 발행 : 2008.10.31
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초록

본 논문에서는 SPD(Sampling Phase Detector) 소자를 위상검출기로 사용하여, 기준 신호원 700 MHz SAW(Surface Acoustic Wave) 발진기에 16.8 GHz의 VTDRO(Voltage Tuned Dielectric Resonator Oscillator)를 안정화하는 위상 고정 회로를 설계하였다. 이러한 위상 고정 방법은 루프 필터만으로 직접적으로 위상 고정할 경우 잠금 시간(lock time)의 문제로, 루프 필터뿐만 아니라 구형파의 시변하는 전류원을 사용 위상 고정하게 된다. 이러한 구동 회로와 루프 필터는 서로 상관 관계가 있어, 이의 체계적인 조정을 필요로 한다. 본 논문에서는 이러한 구동 회로와 루프 필터의 체계적인 설계 방법을 제시하였다. 제작된 PLDRO(Phase Leered DRO)는 안정된 16.8 GHz의 중심 주파수에서 약 6.3 dBm의 출력 전력을 갖고, 위상 잡음은 100 kHz offset에서 -101 dBc/Hz 성능을 보인다.

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.

키워드

참고문헌

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피인용 문헌

  1. Phase Noise Analysis of 2.4 GHz PLL using SPD vol.19, pp.3, 2016, https://doi.org/10.9766/KIMST.2016.19.3.379