ETRI Journal
- Volume 29 Issue 4
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- Pages.457-462
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- 2007
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- 1225-6463(pISSN)
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- 2233-7326(eISSN)
An Experimental 0.8 V 256-kbit SRAM Macro with Boosted Cell Array Scheme
- Chung, Yeon-Bae (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
- Shim, Sang-Won (Memory Division, Samsung Electronics)
- Received : 2006.11.16
- Published : 2007.08.31
Abstract
This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18