DOI QR코드

DOI QR Code

Design and Fabrication Process Effects on Electrical Properties in High Capacitance Multilayer Ceramic Capacitor

고용량 적층 세라믹 커패시터에서 설계 및 제조공정에 따른 전기적 특성 평가

  • 윤중락 (삼화콘덴서공업(주) 연구소) ;
  • 우병철 (삼화콘덴서공업(주) 연구소) ;
  • 이헌용 (호서대학교 정보제어공학과) ;
  • 이석원 (명지대학교 전기공학과)
  • Published : 2007.02.01

Abstract

The purpose of this work was to investigate the design and fabrication process effects on electrical properties in high capacitance multilayer ceramic capacitor (MLCC) with nickel electrode. Dielectric breakdown voltage and insulation resistance value were decreased with increasing stack layer number, but dielectric constant and capacitance were increased. With increasing green sheet thickness, dielectric breakdown voltage, C-V and I-V properties were also increased. The major reasons of the effects were thought to be the defects generated extrinsically during fabrication process and interfacial reactions formed between nickel electrode and dielectric layer. These investigations clearly showed the influence of both green sheet thick ness and stack layer number on the electrical properties in fabricating the MLCC.

Keywords

References

  1. H. Kishi, Y. Mizuno, and H. Chazono, 'Basemetal electrode-multilayer ceramic capacitor: Past, present and future perspectives', Jpn. J. Appl. Phys., Vol. 42, p. 1, 2003 https://doi.org/10.1143/JJAP.42.1
  2. Y. Mizuno, T. Agiwara, H. Chazono, and H. Kishi, 'Effect of milling process on core-shell microstructure and electrical properties for $BaTiO_{3}$-based Ni-MLCC', J. Urop. Ceram. Soc., Vol. 21, p. 1649, 2001 https://doi.org/10.1016/S0955-2219(01)00084-X
  3. Q. U. Feng and C. J. Mcconville, 'Dielectric degradation and microstructures of hetrogeneous interfaces in cofired multilayer ceramic capacitors', J. Electroceram., Vol. 14, p. 213, 2005 https://doi.org/10.1007/s10832-005-0960-9
  4. H. Chazono and H. Kishi, 'dc electrical degradation of the BT based materials for multilayer ceramic capacitor with Ni internal electrode: Impedance analysis and microstructure', Jpn. J. Appl. Phys., Vol. 40, p. 5624, 2001 https://doi.org/10.1143/JJAP.40.5624
  5. 이석원, 윤중락, 'X7R 적층칩 세라믹 캐패시터 조성의 희토류첨가에 따른 유전특성', 전기전자재료학회논문지, 16권, 12호, p. 1080, 2003
  6. 윤중락, 김민기, 이헌용, 이석원, '중,고압용 적층 세라믹 캐패시터 제작 및 분석', 전기전자재료학회논문지, 18권, 8호, p. 685, 2005
  7. Electronic Industries Association, Specification, #RS198

Cited by

  1. Effect of Tm2O3addition on dielectric property of barium titanate ceramics for MLCCs vol.20, pp.1, 2010, https://doi.org/10.6111/JKCGCT.2010.20.1.025