The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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Design and Implementation of Low-Power DCT Architecture by Minimizing Switching Activity

스위칭 엑티비티를 최소화한 저전력 DCT 아키텍쳐 구현

  • 김산 (연세대학교 전기전자공학과 프로세서연구실) ;
  • 박종수 (연세대학교 전기전자공학과 프로세서연구실) ;
  • 이용주 (연세대학교 전기전자공학과 프로세서연구실) ;
  • 이용석 (연세대학교 전기전자공학과 프로세서연구실)
  • Published : 2006.06.01
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Abstract

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of Power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7\sim8%$ without compromising the final DCT results. The proposed low-power DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

저전력 설계는 시스템의 소모전력을 줄임으로써 에너지 절약과 함께 휴대용 장치의 배터리 수명을 극대화시킴에 있어 직면한 가장 중요한 문제이다. 본 논문에서는 개량형 CSHM을 이용하여 저전력 DCT 구조를 제안하였다. 제안된 구조는 Computation Sharing Multiplication 연산 과정 중 불필요한 비트에 대한 연산을 수행하지 않는다. 실험 결과, 기존의 DCT 알고리즘과 동일한 연산 결과를 보이면서도 최대 약 9%의 소모전력이 감소하였다. 따라서 제안된 저전력 DCT 구조는 저전력 및 고성능으로 DCT 알고리즘을 처리해야하는 휴대용 멀티미디어 시스템에 적용이 가능하다.

Keywords

References

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